FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

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FinFETs and Other Multi-Gate Transistors

Metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown impressive performance improvements over the past 10 years by incorporating strained silicon (Si) technology. This review gives an overview of the impact of strain on carrier mobility in Si n- and pMOSFETs by considering strain-induced band splitting, band warping and consequent carrier repopulation, and altered conductivity effective mass and scattering rate. Different surface orientations, channel directions, and gate electric fields are included for a fully theoretical understanding. The results are used to predict strain-enhanced silicon-on-insulator (SOI) and multigate device performance, mainly focusing on potential 22-nm and beyond device options such as double-gate and trigate fin field-effect transistor (FinFET) structures. Insights into strain-enhanced potential future channel materials (SiGe, Ge, and GaAs) are also summarized. Finally, recent technology nodes with strain engineering are reviewed, and the future developing t...

Strain: A Solution for Higher Carrier Mobility in Nanoscale MOSFETs

In this paper, using three-dimensional statistical numerical simulations, the authors study the intrinsic parameter fluctuations introduced by random discrete dopants, line edge roughness (LER), and oxide-thickness variations in realistic bulk MOSFETs scaled to 25, 18, 13 and 9 nm. The scaling is based on a 35 nm MOSFET developed by Toshiba, which has also been used for the calibration of the authors' "atomistic" device simulator. Special attention is paid to the accurate resolution of the individual discrete dopants in the drift-diffusion simulations by introducing density-gradient quantum corrections for both electrons and holes. In the LER simulations, two scenarios have been adopted: in the first one, LER follows the prescriptions of the International Roadmap for Semiconductors; in the second one, LER is kept constant close to the current best values. Combined effects of the different sources of intrinsic parameter fluctuations have also been simulated in the 35 nm reference devices and the results for the standard deviation of the threshold voltage compared to the measured values

http://userweb.eng.gla.ac.uk/andrew.brown/papers/IEEE_TED_2006_Scaled_Devices.pdf

Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs

A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

Recessed Si/sub 0.8/Ge/sub 0.2/ source/drain (S/D) and a compressive contact etch-stop layer have been successfully integrated resulting in nearly 200% improvement in hole mobility. This is the largest reported process-induced hole mobility enhancement to the authors' knowledge. This letter demonstrates that a drive-current improvement from recessed Si/sub 0.8/Ge/sub 0.2/ plus the compressive nitride layer are in fact additive. Furthermore, it shows that the mobility enhancement is a superlinear function of stress, leading to larger than additive gains in the drive current when combining several stress sources.

pMOSFET with 200% mobility enhancement induced by multiple stressors

This paper presents the low-frequency noise (LFN) behavior of vertical tunnel FETs (TFETs). The experimental input characteristics with different source compositions (Si and Ge) and different HfO2 thicknesses in the gate-stack (2 and 3 nm) are presented. A brief analog parameters analysis, including the transconductance, output conductance, and intrinsic voltage gain behavior under different bias conditions, shows that TFETs are promising for analog applications. For the LFN study, the standard number fluctuations model for MOSFETs was used in order to verify and compare the TFETs noise behavior, exploring the influence of different conduction mechanisms in each bias region. In the proposed model, the effective channel length ( $L_{\mathrm{eff}}$ ) is replaced by the tunneling length, resulting in good agreement between the experimental data and the model. The temperature influence on the TFET noise behavior is also investigated.

Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source

In this letter, we investigate the influence of tensile and compressive SiN layers on the device performance of triple-gate devices with 60-nm fin height and fin widths down to 35 nm. It will be shown that even for narrow fin devices, the nMOS performance improvement can be as high as 20% with tensile strained layers. The improvement seen for pMOS is lower, about 10%. Next to that both compressive as well as tensile SiN layers can increase the pMOS on-state current.

Performance improvement of tall triple gate devices with strained SiN layers

FinFETs are known to be one of the most promising technological solutions to create high-performance ultra-scaled Si MOSFETs. In this paper, we present the first detailed experimental investigation of the analog performance of FinFETs with channel lengths down to 50 nm. We demonstrate that such devices have very strong potential for analog applications, mainly thanks to a super-high value of the Early voltage and hence intrinsic gain, which they can provide. The impact of fin width on device characteristics is also analysed. We show that the narrowest devices appear as the most promising, since they operate in the fully-depleted regime, even possibly in volume inversion.

Perspective of FinFETs for analog applications

In this work, we have compared different FB-RAM architectures. Whereas highly doped PDSOI devices show high programming window and retention times for long channel devices, the SOI FinFET devices with WFIN=25 nm can be scaled down to LG=50 nm while still maintaining high cell margins and retention times. For the latter devices optimization of the write and especially read bias conditions is needed.

Rita Rooyackers

Papers

pMOSFET with 200% mobility enhancement induced by multiple stressors

Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source

Performance improvement of tall triple gate devices with strained SiN layers

Perspective of FinFETs for analog applications

Comparison of scaled floating body RAM architectures