Showing papers by "Robert M. Wallace published in 2004"

Diffusion Studies of Copper on Ruthenium Thin Film A Plateable Copper Diffusion Barrier

Abstract: Diffusion studies were carried out on physical vapor deposited Cu/Ru(∼20 nm)/Si samples using secondary ion mass spectroscopy (SIMS) and transmission electron microscopy (TEM). Back side SIMS depth profiling revealed well-defined interfaces and showed that Cu interdiffusion was impeded by Ru thin film up to 450°C vacuum annealing. TEM showed a 20-22 nm Ru barrier layer with a columnar microstructure oriented vertically with respect to Si substrate. TEM results corroborate with SIMS data to indicate stability of the Ru film barrier for annealing temperatures up to 450°C. Direct Cu electroplating on ultrathin Ru barrier layers (<20 nm) was investigated in sulfuric acid. The electroplated Cu film is shiny, smooth, and without agglomeration under scanning electron microscopy. Excellent adhesion between interfacial layers was confirmed by the scribe-peel test. The interfacial characterization results indicate that Ru thin film is a promising candidate as a directly plateable Cu diffusion barrier.

A novel methodology on tuning work function of metal gate using stacking bi-metal layers

Abstract: We demonstrate that the work function of a metal gate can be varied by inserting a very thin metal layer ("metal A") between a thick metal ("metal B") and the gate dielectric. The flat band voltage (VFB) of the MOS (metal-oxide-semiconductor) capacitor structure can be controlled within the range bounded by metal A and metal B individually, as demonstrated with various stacked bi-metal layers. For continuous thin layers, we speculate that the work function tunability may be due to the drastic change of the electron density in the thin continuous metal layer in direct contact with a bulk metal. This drastic change of electron density results in a larger junction depth than that expected for a bulk metal. Non-uniform thin layers also appear effective for work function tuning as well, and the observed VFB shift is attributed to the metal island formation at the dielectric/metal A interface.

High permittivity silicate gate dielectric

Abstract: A field effect semiconductor device comprising a high permittivity silicate gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A metal silicate gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38 . Silicate layer 36 may be, e.g., hafnium silicate, such that the dielectric constant of the gate dielectric is significantly higher than the dielectric constant of silicon dioxide. However, the silicate gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability. The present invention includes methods for depositing both amorphous and polycrystalline silicate layers, as well as graded composition silicate layers.

Underpotential deposition of copper on electrochemically prepared conductive ruthenium oxide surface

Abstract: Copper underpotential deposition (UPD) on a conductive hydrous ruthenium oxide (RuO x H y ) surface was studied by progressive cyclic voltammetry and X-ray photoelectron spectroscopy (XPS). Cu UPD on an electrochemically prepared RuO x H y surface started at 0.15 V in a 2 mM CuSO 4 solution and reached a coverage plateau of ca. 0.9 monolayer (ML) beyond -0.05 V (vs. Ag/AgCl). XPS data confirmed that Cu deposits underpotentially on RuO x H y surface. The anodic polarization potential determines the chemical states and affects the Cu UPD/bulk deposition of RuO x H y electrode. We observed close to a 55% increase of underpotential shift for Cu UPD on RuO x H y (ca. 170 mV) in comparison to Ru surface (ca. 110 mV). The results suggest that interfacial binding of the first ML of Cu on RuO x H y is stronger than Ru by 12 kJ mol - 1 . Possible applications of Cu UPD to Ru-based plateable seedless Cu diffusion barrier are discussed.

Hydrogen and deuterium incorporation and transport in hafnium-based dielectric films on silicon

Abstract: Hydrogen and deuterium incorporation into nitrided and non-nitrided hafnium silicate films on Si during thermal annealing in H1- and H2-containing atmospheres was investigated. H1 profiling was accessed by means of nuclear resonant reaction profiling, whereas H2 incorporation was quantified by nuclear reaction analysis. The effects of preannealing in different atmospheres and temperatures were determined, as well as the losses of H1 and H2 from these structures during postannealing in vacuum. The results reveal a rather uniform depth distribution of incorporated H1, in striking contrast with previous studies on hydrogen in silicon oxide and oxynitrides and hafnium oxide films on Si. These results are discussed in terms of the defects present in each one of the structures studied here.

Thermal stability of Hf-based high-k dielectric films on silicon for advanced CMOS devices

Abstract: HfSiON and HfSiO films deposited on Si(1 0 0) by reactive sputtering followed by UV/ozone oxidation were submitted to different sequential rapid thermal annealings in N2 and/or O2 atmospheres. The thermal stability of the system was addressed by determining the atomic transport and exchange of the involved chemical species using nuclear reaction analysis, nuclear resonance profiling and X-ray photoelectron spectroscopy. We investigated the effects of pre-annealing in N2 prior to O2 annealing, which leads to a decrease in oxygen diffusivity through the films. This effect was also observed in a thermal annealed HfSiO/HfSiO15N/Si structure, where the nitrogenous species present only in the intermediate layer stops the oxygen diffusion. Film growth was observed in both HfSiO and HfSiON samples. The growth is due to oxygen incorporated during thermal annealings that reacts with substrate-Si. Annealing in 15N2 promotes nitrogen incorporation only in HfSiON samples, indicating an incorporation mechanism based on isotopic exchange between 14N and 15N. We observed by XPS that the incorporated oxygen is changing the chemical environment of the film.

Low-temperature deposition of hafnium silicate gate dielectrics

Abstract: The physical and electrical properties of hafnium silicate (HfSi/sub x/O/sub y/) films produced by low-temperature processing conditions (/spl les/150/spl deg/C) suitable for flexible display applications were studied using sputter deposition and ultra-violet generated ozone treatments. Films with no detectable low-/spl kappa/ interfacial layer were produced. Rutherford backscattering spectroscopy, X-ray photoelectron spectroscopy, and high-resolution transmission electron microscopy were used to determine the composition, chemical bonding environment, thickness, and film interface. The electrical behavior of the as-deposited and annealed hafnium silicate films were determined by current-voltage (I--V) and capacitance-voltage (C--V) measurements.

Growth and characterization of hafnium silicate films prepared by UV/ozone oxidation

Abstract: Physical and electrical properties of hafnium silicate (HfSixOy) dielectric films prepared by room-temperature UV/ozone (O3) oxidation of hafnium silicide (HfSi2) are reported. Angle-resolved x-ray photoelectron spectroscopy was used to determine chemical bonding at the film interface and within the bulk film. These films, with 12 at. % Hf composition, have a dielectric constant (κ) of ∼8–9 and exhibit a flat-band voltage shift of 60 mV. The leakage current density at VFB+1 V is 4.7×10−5 A/cm2 for a 4.7-nm-thick film (capacitance equivalent thickness=2.6 nm) and breakdown strength was >8 MV/cm.

Deposition of Hf–silicate gate dielectric on SixGe1−x(100): Detection of interfacial layer growth

Abstract: The deposition of a stable high-κ dielectric material such as hafnium silicate in direct contact with strained epitaxial SixGe1−x(100) layers on Si(100) provides the prospect of eliminating the Si buffer layer that is currently used to form the gate oxide in SiGe-based devices. In this study, ∼3-nm-thick hafnium silicate films were produced by sputter deposition of hafnium silicide films on precleaned SixGe1−x(100), with subsequent UV-O3 oxidation at room temperature. Prolonged UV-O3 exposure at room temperature leads to the growth of an interfacial layer comprised of a mixture of silicon and germanium oxides. We report on the use of x-ray photoelectron spectroscopy, particularly the x-ray excited Ge (L3MM) Auger feature to optimize UV-O3 exposure time, and minimize the interfacial layer growth of silicon and germanium oxides.

The electrical properties and stability of the hafnium silicate/Si0.8Ge0.2(100) interface

Abstract: The effect of post-oxidation N2 annealing and post-metallization forming-gas annealing on the electrical properties of Pt/Hf-silicate (3 nm)/Si0.8Ge0.2(100)/n-type Si(100) metal-oxide semiconductor (MOS) capacitors is reported. Capacitance-voltage (C-V) and current density-voltage (J-V) measurements of asgrown, 3-nm-thick, hafnium-silicate films containing ∼12at.%Hf indicate a large number of bulk and interface traps with a current density of ∼10−2 A/cm2 at VFB+1 V. Post-ultraviolet (UV)/O3 oxidation annealing in N2 at 350°C for 30 min leads to a significant improvement in the electrical characteristics of the film. A post-metallization anneal (PMA) at 450°C for 30 min in forming gas (90% N2:10% H2), however, degraded the electrical properties of the films. X-ray photoelectron spectroscopy (XPS) analyses of the forming-gas-annealed films indicate that a possible cause for the degradation in electrical properties is the hydrogen-induced reduction of GeO2 in the interfacial SixGe1−xO2 oxide layer to elemental germanium. Implications for the introduction of hafnium silicate as a viable gate dielectric for SiGe-based devices are discussed.

Nano-patterning and manipulation of genetically engineered virus nanoblocks

Abstract: Over the past several years there have been extensive research efforts on molecular electronics [1]. For the fabrication of molecular electronic devices, one type of hierarchical directed self-assembly process based on a plant virus particle (referred to as a virus nanoblock or VNB) is of great interest [2]. In this paper, we present results on the controlled 3-dimensional organization of 5nm gold nanoparticles at specific sites, using the Cowpea Mosaic Virus (CPMV) as a template, and also on the nanomanipulation of virus nanoblocks for electrical properties measurements.