다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage ( $\mathrm{V}_{\rm DD}$ ). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at $\mathrm{L}_{\rm G}= 13$ nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional $\mathrm{V}_{\rm DD}$ . Also, P-TFET current-drive is between $1\times $ to $0.5\times $ of N-TFET, depending on choice of $\mathrm{I}_{\rm OFF}$ and $\mathrm{V}_{\rm DD}$ . There are many challenges to realizing TFETs in products, such as the requirement of high quality III–V materials and oxides with very thin body dimensions, and the TFET’s layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.

Tunnel Field-Effect Transistors: Prospects and Challenges

Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

Process Technology Variation

Two-dimensional (2D) semiconductors have attracted tremendous interest as atomically thin channels that could facilitate continued transistor scaling. However, despite many proof-of-concept demonstrations, the full potential of 2D transistors has yet to be determined. To this end, the fundamental merits and technological limits of 2D transistors need a critical assessment and objective projection. Here we review the promise and current status of 2D transistors, and emphasize that widely used device parameters (such as carrier mobility and contact resistance) could be frequently misestimated or misinterpreted, and may not be the most reliable performance metrics for benchmarking 2D transistors. We suggest that the saturation or on-state current density, especially in the short-channel limit, could provide a more reliable measure for assessing the potential of diverse 2D semiconductors, and should be applied for cross-checking different studies, especially when milestone performance metrics are claimed. We also summarize the key technical challenges in optimizing the channels, contacts, dielectrics and substrates and outline potential pathways to push the performance limit of 2D transistors. We conclude with an overview of the critical technical targets, the key technological obstacles to the 'lab-to-fab' transition and the potential opportunities arising from the use of these atomically thin semiconductors.

Promises and prospects of two-dimensional transistors

In this paper, the NBTI-induced circuit frequency degradation is found having a non-monotonic bias dependence, thus an optimal V DD can be assessed based on this reliability tradeoff. As a demonstration, based on our recently-developed compact aging model and circuit reliability simulator, NBTI-induced frequency degradation in inverters are simulated, in terms of various V th and V DD , considering two typical stress waveforms. The results show the relationships between the optimal V DD of circuit and various stress conditions, which are useful to the reliability-aware V DD optimization for CMOS technology.

Optimal V DD Assessment of CMOS Technology Considering Circuit Reliability Tradeoffs

In this paper, based on the quantitatively characterized factor of channel current percolation path (PP), the local current fluctuations characteristics in device channel can be directly determined by I-V curves only, which links the microscopic PPs to macroscopic device electrical parameters. The results indicate that the newly-defined “killer ratio” of PP is highly correlated with subthreshold swing degradation rate in both planar devices and FinFETs. It is also found that the current in PP area increases slower with V_{g} than the current in non-PP area, which is verified through TCAD and SPICE simulations. The explanation of the physical nature of correlated behavior sheds new light on understanding statistical variability and reliability in nanoscale devices.

Study on the Direct Relationship between Macroscopic Electrical Parameters and Microscopic Channel Percolative Properties in Nanoscale MOSFETs

A method is proposed to realize NOR logic. Unlike existing solutions, the new solution has no requirements on unrealistic device characteristics such as high asymmetry to operating voltages or the small variations. By comprehensive analysis and the fabrication of Cu-based conductive-bridge- RAM, we show the reliably implementation, which paves ways for future low-power reconfigurable computing.

Realization of NOR logic using Cu/ZnO/Pt CBRAM

In this paper, we observed non-negligible body bias effect after hot carrier degeneration (HCD) in 7 and 5nm FinFET technologies, even though they have negligible body bias dependence before HCD. We revealed that the trap-induced partial shift of the channel current towards the bottom of fin is the culprit for the enhanced body-biased effect, by combining TCAD and experimental results. We also studied mobility modulation by body bias effect before and after degradation. The results are beneficial for the reliability-aware circuit design against HCD particularly for FinFET-based circuits.

Investigation of Hot Carrier Enhanced Body Bias Effect in Advanced FinFET Technology

Deep neural networks (DNNs) have revolutionized different applications ranging from computer vision to natural language processing, and are widely deployed in data centers and edge devices. It can be foreseen that DNNs will be applied in more and more safety-critical applications like autonomous driving and robotics, which typically require highly reliable computing to avoid catastrophic consequences. Therefore, not only the model's robustness against various perturbations like adversarial noise, but also the robustness of the silicon-based accelerators to hardware faults needs to be comprehensively investigated [1], [2].

Runsheng Wang

Papers

Optimal V DD Assessment of CMOS Technology Considering Circuit Reliability Tradeoffs

Study on the Direct Relationship between Macroscopic Electrical Parameters and Microscopic Channel Percolative Properties in Nanoscale MOSFETs

Realization of NOR logic using Cu/ZnO/Pt CBRAM

Investigation of Hot Carrier Enhanced Body Bias Effect in Advanced FinFET Technology

READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction