다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage ( $\mathrm{V}_{\rm DD}$ ). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at $\mathrm{L}_{\rm G}= 13$ nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional $\mathrm{V}_{\rm DD}$ . Also, P-TFET current-drive is between $1\times $ to $0.5\times $ of N-TFET, depending on choice of $\mathrm{I}_{\rm OFF}$ and $\mathrm{V}_{\rm DD}$ . There are many challenges to realizing TFETs in products, such as the requirement of high quality III–V materials and oxides with very thin body dimensions, and the TFET’s layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.

Tunnel Field-Effect Transistors: Prospects and Challenges

Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

Process Technology Variation

Two-dimensional (2D) semiconductors have attracted tremendous interest as atomically thin channels that could facilitate continued transistor scaling. However, despite many proof-of-concept demonstrations, the full potential of 2D transistors has yet to be determined. To this end, the fundamental merits and technological limits of 2D transistors need a critical assessment and objective projection. Here we review the promise and current status of 2D transistors, and emphasize that widely used device parameters (such as carrier mobility and contact resistance) could be frequently misestimated or misinterpreted, and may not be the most reliable performance metrics for benchmarking 2D transistors. We suggest that the saturation or on-state current density, especially in the short-channel limit, could provide a more reliable measure for assessing the potential of diverse 2D semiconductors, and should be applied for cross-checking different studies, especially when milestone performance metrics are claimed. We also summarize the key technical challenges in optimizing the channels, contacts, dielectrics and substrates and outline potential pathways to push the performance limit of 2D transistors. We conclude with an overview of the critical technical targets, the key technological obstacles to the 'lab-to-fab' transition and the potential opportunities arising from the use of these atomically thin semiconductors.

Promises and prospects of two-dimensional transistors

A new body-on-insulator (BOI) FinFET device structure based on bulk-Si substrate has been proposed and experimentally demonstrated in this paper. In comparison with other bulk FinFETs, the BOI FinFET features the localized insulator below the Si-Fin body, which can achieve both low source/drain (S/D) parasitic resistance and effective suppression of the S/D leakage beneath the Si-Fin channel, as well as good heat dissipation capability. The device fabrication process is basically compatible with conventional CMOS technology. High drive current, low subthreshold swing, and excellent short-channel behavior are observed in the fabricated BOI FinFETs.

High-Performance BOI FinFETs Based on Bulk-Silicon Substrate

In this paper, the major physical effects caused by gate oxide traps in MOSFETs have been integrated for the first time by a proposed unified approach in realistic manners based on industry-standard EDA tools, aiming at practical trap-aware device/circuit co-design. The recently-found AC or transient effects of traps and the interplays with manufacturing process variations are included, with demonstrations on two representatives (RO and SRAM) under realistic digital circuit operations. The proposed approach and the results are helpful for robust and resilient device/circuit co-design in future nano-CMOS technology.

https://cseweb.ucsd.edu/~muluo/publications/06724745.pdf

A unified approach for trap-aware device/circuit co-design in nanoscale CMOS technology

The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices at the end of the technology roadmap. This paper reviews our recent work on the characterization and analysis of this unique one-dimensional nanowire-channel device with three-dimensional surrounding-gate from experiments and simulation, including carrier transport behavior, parasitic effects, noise characteristics, self-heating effect, variability and reliability, which can provide useful information for the GAA device hierarchical modeling and device/circuit co-design.

Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling

As the generally-accepted simple understanding, the random telegraph noise (RTN) induced by a single trap is explained by the “normal” two-state trap model, and the RTNs caused by two or more traps in one device are regarded as the independent superposition effect of these traps While in real cases, both the above points cannot illustrate many complex RTN (cRTN) results in practice In this paper, two categories of complex RTNs, which are induced by the metastable trap-states and the trap coupling effect, respectively, are investigated based on experimental results in detail The RTN with metastable states are explained based on the observed “anomalous” RTN data The physical mechanisms of the trap coupling effect on RTN amplitudes and time constants are studied based on experiments The results are helpful for comprehensive understanding and modeling of RTN and switching traps, thus is useful for the accurate evaluation on the impacts of RTN on nanoscale CMOS devices and circuits

Complex Random Telegraph Noise (RTN): What Do We Understand?

Device variability and reliability are becoming increasingly important for nano-CMOS technology and circuits, due to the shrinking circuit design margin with the downscaling supply voltage (V dd ) Therefore, robust design should have the awareness of both variability and reliability In FinFET technology, strong correlation between the variations of device electrical parameters is found, due to the larger impacts of line-edge roughness (LER) in FinFET structure Accurate compact models and new design methodology for random variability in FinFETs were proposed for the variation-and correlation-aware design For the reliability awareness, the impacts of BTI-induced temporal shift and the layout dependent aging effects should be taken into account for the optimization of end-of-life (EOL) performance/power/area (PPA) New-generation aging model and circuit reliability simulator for FinFETs were proposed and developed in industry-standard EDA tools Future challenges are also pointed out, such as statistical BTI and RTN The results are helpful for the robust and resilient design for 16/14nm and beyond

Runsheng Wang

Papers

High-Performance BOI FinFETs Based on Bulk-Silicon Substrate

A unified approach for trap-aware device/circuit co-design in nanoscale CMOS technology

Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling

Complex Random Telegraph Noise (RTN): What Do We Understand?

Variability-and reliability-aware design for 16/14nm and beyond technology