다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage ( $\mathrm{V}_{\rm DD}$ ). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at $\mathrm{L}_{\rm G}= 13$ nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional $\mathrm{V}_{\rm DD}$ . Also, P-TFET current-drive is between $1\times $ to $0.5\times $ of N-TFET, depending on choice of $\mathrm{I}_{\rm OFF}$ and $\mathrm{V}_{\rm DD}$ . There are many challenges to realizing TFETs in products, such as the requirement of high quality III–V materials and oxides with very thin body dimensions, and the TFET’s layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.

Tunnel Field-Effect Transistors: Prospects and Challenges

Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

Process Technology Variation

Two-dimensional (2D) semiconductors have attracted tremendous interest as atomically thin channels that could facilitate continued transistor scaling. However, despite many proof-of-concept demonstrations, the full potential of 2D transistors has yet to be determined. To this end, the fundamental merits and technological limits of 2D transistors need a critical assessment and objective projection. Here we review the promise and current status of 2D transistors, and emphasize that widely used device parameters (such as carrier mobility and contact resistance) could be frequently misestimated or misinterpreted, and may not be the most reliable performance metrics for benchmarking 2D transistors. We suggest that the saturation or on-state current density, especially in the short-channel limit, could provide a more reliable measure for assessing the potential of diverse 2D semiconductors, and should be applied for cross-checking different studies, especially when milestone performance metrics are claimed. We also summarize the key technical challenges in optimizing the channels, contacts, dielectrics and substrates and outline potential pathways to push the performance limit of 2D transistors. We conclude with an overview of the critical technical targets, the key technological obstacles to the 'lab-to-fab' transition and the potential opportunities arising from the use of these atomically thin semiconductors.

Promises and prospects of two-dimensional transistors

The smart edge nodes require efficient matrix-vector multiplications for local deep neural network (DNN) inference. Benefiting from its high density and CMOS compatibility, the eDRAM-based computing-in-memory (CIM) [1] –[4], especially with multi-level cells (MLCs) [4], attracts rising attention. However, the performance of prior MLCeDRAM CIM is severely limited by the inconsistency of weight representations during the programming and computing: weights are programmed as fixed voltages while transistor currents are used for computation. Thus, the programming of MLCs requires calibration due to the nonlinear transistor I-V, which can be extremely complicated in the presence of $V_{T H}$ variations. Furthermore, the computing precision is severely degraded by $\mathrm{V}_{\mathrm{TH}}$ variations when small computing currents are used for high parallelism. To fundamentally surmolunt this dilemma, we propose the first currentprogramming eDRAM CIM that unifies the weight programming and computing in the current domain. The enabling technique is a novel 3T1C eDRAM cell (Fig. 1, top right). It confers several key merits: 1) the cell is programmed by the weight current directly with the selfcalibrated voltage generated on the storage capacitor; it essentially stores the weight current instead of a fixed voltage, thus mitigating $V_{\text {TH}}$ variation and nonlinear transistor I-V impacts; 2) a dynamiccascoded read structure is proposed to significantly reduce the VB sensitivity while not requiring any bias voltage; 3) thanks to the accurately programmed cell, it supports MLC operation (8 current levels) without any calibration, largely increasing density; 4) a voltage-current two-step programming scheme significantly boosts the sub- $\mu \mathrm{A}$ current-weight writing speed. Combining these merits, the proposed eDRAM cell is naturally immune to transistor-level nonidealities, thus allowing a small LSB weight current of only 100nA. A $4 \mathrm{~b}$ CIM cell composed of 2MLCs is developed to support 4bsigned weights. It contains 15 current levels ranging from -700nA to 700nA. Fabricated in a $65 \mathrm{~nm}$ CMOS, the prototype achieves the highest macro-level 4b-MAC energy efficiency of 233-305TOPS/W among eDRAM CIMs.

A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC

pFETs fabricated with the sub-20nm technology are investigated under hot carrier stress conditions of the gate voltage (|Vg|) lower than the drain voltage (|Vd|). Two types of defects are identified: the interface states generation exhibits the positive charge formation while the electron-traps lead to the negative charge accumulation. The corresponding energy levels and the spatial locations are identified by exploring the defect-induced mobility degradation and the recovery phenomenon. Finally, a defect-based model is proposed for both the threshold voltage shift and the mobility degradation, which allows the full IV to be predicted after aging. Thus the work paves ways for future device/circuit co-optimization in DRAM peripheral circuits.

Characterization and Modelling of Hot Carrier Degradation in pFETs under Vd>Vg Condition for sub-20nm DRAM Technologies

Mobility degradation due to generation of defects is a well-known phenomenon. Split C~V technique is the most widely used experimental method. However, this technique can induce large error in the presence of generated fast states: they can distort the split C~V technique and lead to over-estimation of the mobile channel carriers. As a consequence, mobility degradation will be over-estimated. Accurate determination of the mobility after degradation is critical for time-dependent reliability modeling. In this work, for the first time, a new "Shift and Match" (S&M) method is proposed to determine these generated fast states based on experimentally measured I d ~V g , C gc ~V g and C gb ~V g data. The potential sources of error in this new method, including series resistance have been investigated. Based on this method, hole mobility degradation has been re-evaluated on pMOSFET after NBTI stress. It is found that mobility degradation can be over-estimated by more than 50%.

“Shift and Match” (S…M) method for channel mobility correction in degraded MOSFETs

The design automation community has been actively exploring machine learning for VLSI CAD. Many studies have explored learning-based techniques for cross-stage prediction tasks in the design flow. Although building machine learning models usually requires a large amount of data, most studies can only generate small internal datasets for validation due to the lack of large public datasets. Such a situation challenges the research in this field and raises potential issues like difficulty in benchmarking and reproducing results, limited research scope on small internal datasets, and high bar for new researchers. Therefore, in this paper, we present an open-source dataset called “CircuitNet” for machine learning tasks in VLSI CAD. The dataset consists of more than 10K samples extracted from versatile runs of commercial design tools based on 6 open-source RISC-V designs which support typical cross-stage prediction tasks, such as routability and IR drop prediction, with extensive benchmarking on recent models. With the dataset prepared, we identify two practical challenges, data imbalance and model transferability, for machine learning application in CAD. To overcome data imbalance, we propose a loss function, biased loss, to give more weight to the minority, leading to 2% congestion reduction in routability driven placement. We test the model transferability from RISC-V designs to ISPD 2015 contest designs in congestion prediction with several transfer learning methods, and further proposed a knowledge distillation based transfer learning framework with up to 20% accuracy improvement. We believe this dataset can open up new opportunities for machine learning in CAD research and beyond. 

CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications with Improved Domain-Specific Evaluation Metric and Learning Strategies

With the downscaling of CMOS technology, the reliability issue has become inevitable. Even in fault-tolerant applications, the effects of timing violation caused by the transistor aging are unacceptable. In the past, the traditional method to solve timing violation is to add a wide frequency guardband, which will lead to the decrease of speed. In this paper, the reliability of the approximate computing is evaluated in an image processing applications. And a method to improve circuit reliability is proposed. The results show that this method can turn critical path timing errors, which are difficult to predict and seriously hurt circuit reliability, into deterministic logic simplification errors, and thus the actual function of the circuit is not affected.

Runsheng Wang

Papers

A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC

Characterization and Modelling of Hot Carrier Degradation in pFETs under Vd>Vg Condition for sub-20nm DRAM Technologies

“Shift and Match” (S…M) method for channel mobility correction in degraded MOSFETs

CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications with Improved Domain-Specific Evaluation Metric and Learning Strategies

Circuit Reliability Evaluation of Approximate Computing