Runsheng Wang

TL;DR: In this article, the silicon nanowire transistor (SNWT)-based circuits of current mirrors (NWCMs) have been successfully fabricated for the first time, and the key figures of merit of current mirror (CMs) are experimentally studied, including output voltage coefficient (OVC), output resistance, and dc matching error e.g.

TL;DR: In this article, the negative bias temperature instability (NBTI) characteristics of silicon nanowire transistors with metal gates were experimentally studied and it was demonstrated that large amounts of as-grown defects, including both electron traps and hole traps, are induced by nanometre structure due to multiple surface crystal orientations of the cylinder nanowires.

TL;DR: In this paper, a new methodology of near-threshold voltage (NTV) design optimization for FinFET is proposed for the first time, and demonstrated based on silicon data, and the proposed methodology is then demonstrated under Vdd =199mV and Vdd=145mV, targeting energy-efficiency priority and V dd priority, respectively.

TL;DR: In this paper, the authors report high-speed ultrathin-body (3.5 nm) indium-tin-oxide (ITO) transistors using high-k HfLaO dielectrics with a thickness of 5 nm.

TL;DR: In this article, the authors improved the characterization method based on clustering and Hidden Markov Model, which greatly enhances the ability to extract RTN with non-negligible "ghost noise" in high-κ MOSFETs.