Runsheng Wang

TL;DR: In this paper, a dual-edge single input (DESI) TD computing topology is proposed, which can significantly improve the area and power efficiencies of TD cell and support binary DNNs.

TL;DR: In this article, the lateral trap distributions in planar and FinFET devices were experimentally studied under various bias stress conditions of hot-carrier degradation (HCD), and it was found that the peak of the trap distribution profile will gradually move closer to the source region with the increase in the HCD stress.

TL;DR: In this article, the defect coupling effect between multi-traps in complex RTN was experimentally studied in scaled high-κ/metal-gate MOSFETs for the first time.

TL;DR: In this paper, the dynamic variability induced by hot carrier degradation (HCD) in FinFETs with decomposing the variation contributions of multiple types of traps is studied with a circuit simulation.

TL;DR: This study unearths the fundamental defect-driven interfacial electric structure of III-V semiconductor materials and paves the way to future high-speed and high-reliability devices.