다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage ( $\mathrm{V}_{\rm DD}$ ). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at $\mathrm{L}_{\rm G}= 13$ nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional $\mathrm{V}_{\rm DD}$ . Also, P-TFET current-drive is between $1\times $ to $0.5\times $ of N-TFET, depending on choice of $\mathrm{I}_{\rm OFF}$ and $\mathrm{V}_{\rm DD}$ . There are many challenges to realizing TFETs in products, such as the requirement of high quality III–V materials and oxides with very thin body dimensions, and the TFET’s layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.

Tunnel Field-Effect Transistors: Prospects and Challenges

Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

Process Technology Variation

Two-dimensional (2D) semiconductors have attracted tremendous interest as atomically thin channels that could facilitate continued transistor scaling. However, despite many proof-of-concept demonstrations, the full potential of 2D transistors has yet to be determined. To this end, the fundamental merits and technological limits of 2D transistors need a critical assessment and objective projection. Here we review the promise and current status of 2D transistors, and emphasize that widely used device parameters (such as carrier mobility and contact resistance) could be frequently misestimated or misinterpreted, and may not be the most reliable performance metrics for benchmarking 2D transistors. We suggest that the saturation or on-state current density, especially in the short-channel limit, could provide a more reliable measure for assessing the potential of diverse 2D semiconductors, and should be applied for cross-checking different studies, especially when milestone performance metrics are claimed. We also summarize the key technical challenges in optimizing the channels, contacts, dielectrics and substrates and outline potential pathways to push the performance limit of 2D transistors. We conclude with an overview of the critical technical targets, the key technological obstacles to the 'lab-to-fab' transition and the potential opportunities arising from the use of these atomically thin semiconductors.

Promises and prospects of two-dimensional transistors

The silicon nanowire MOSFET (SNWT) with gate-all-around (GAA) architecture has exhibited great potential in high-performance nano-electronics applications [1–4]. However, line-edge roughness (LER) induced by lithography and etching processes has become a critical concern for decananometer MOSFETs, because it does not scale accordingly with line widths [5]. Especially, the LER of nanowires, which contains two degrees of freedom rather than one in the traditional planar devices, may have different and intriguing effect on SNWTs. Therefore, performance variation of SNWTs induced by nanowire-LER may become a great challenge to scalability and stability of SNWT-based ICs, where 2-D geometrical fluctuation becomes an even more serious problem in nano-scale. Yet, only few preliminary studies on such impact have been reported [6]. In this paper, a full 3-D statistical investigation is performed, based on the measured LER from SEM images, to estimate the impact of nanowire-LER on SNWTs, including both DC and analog/RF performance. The results can provide guidelines for process optimization as well as robust design of SNWT-based circuits.

Investigation on the effective immunity to process induced line-edge roughness in silicon nanowire MOSFETs

Previous works on transistor reliability are mostly devoted to ON-state degradations, such as bias temperature instability and hot carrier degradation, for which physical models have been developed to describe corresponding mechanisms. However, very limited data on OFF-state degradation is available, especially in FinFET technology. In the first part of this article, OFF-sate degradations of 7-nm FinFET technology are reported for the first time. The physics mechanisms in OFF-state degradation are proposed by combining TCAD simulations and comprehensive experimental characterizations. It is found that an enhanced secondary carriers effect is responsible for the OFF-state degradation with contributions from both trapped electrons and holes. Furthermore, typical locations of electron traps and hole traps under the OFF-state degradation are identified. The abnormal leakage degradation is explained in a consistent manner. The analysis here leads to a compact reliability model reported in part II.

Investigation of the Off-State Degradation in Advanced FinFET Technology—Part I: Experiments and Analysis

Convolutional neural networks (CNN) have achieved excellent performance on various tasks, but deploying CNN to edge is constrained by the high energy consumption of convolution operation. Stochastic computing (SC) is an attractive paradigm which performs arithmetic operations with simple logic gates and low hardware cost. This paper presents an energy-efficient mixed-signal multiply-accumulate (MAC) engine based on SC. A parallel architecture is adopted in this work to solve the latency problem of SC. The simulation results show that the overall energy consumption of our design is 5.03pJ per 26-input MAC operation under 28nm CMOS technology.

An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing

For neural network (NN) applications at the edge of AI, computing-in-memory (CIM) demonstrates promising energy efficiency. However, when the network size grows while fulfilling the accuracy requirements of increasingly complicated application scenarios, significant memory consumption becomes an issue. Model pruning is a typical compression approach for solving this problem, but it does not fully exploit the energy efficiency advantage of conventional CIMs, because of the dynamic distribution of sparse weights and the increased data movement energy consumption of reading sparsity indexes from outside the chip. Therefore, we propose a vector-wise dynamic-sparsity controlling and computing in-memory structure (DS-CIM) that accomplishes both sparsity control and computation of weights in SRAM, to improve the energy efficiency of the vector-wise sparse pruning model. Implemented in a 65 nm CMOS process, the measurement results show that the proposed DS-CIM macro can save up to 50.4% of computational energy consumption, while ensuring the accuracy of vector-wise pruning models. The test chip can also achieve 87.88% accuracy on the CIFAR-10 dataset at 4-bit precision in inputs and weights, and it achieves 530.2TOPS/W (normalized to 1 bit) energy efficiency.

A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling

The complexity of Random Telegraph Noise (RTN) under digital circuit operations makes it difficult to predict its impacts without accurate modeling and simulation. However, properly integrating RTN into circuit simulation is challenging due to its stochastic nature. In this paper, RTN is comprehensively modeled and embedded into BSIM. A circuit simulation methodology based on industry-standard EDA tools is proposed, resolving the stochastic property, the AC effects, and the coupling of RTN and circuits that are crucial for accurate predictions of impacts of RTN. Using the compact model and proposed method, impacts of RTN on RO and SRAM are demonstrated, which ascertains their applicability to different type of circuits.

/pdf/compact-modeling-of-random-telegraph-noise-in-nanoscale-55fxb3wk54.pdf

Runsheng Wang

Papers

Investigation on the effective immunity to process induced line-edge roughness in silicon nanowire MOSFETs

Investigation of the Off-State Degradation in Advanced FinFET Technology—Part I: Experiments and Analysis

An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing

A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling

Compact modeling of Random Telegraph Noise in nanoscale MOSFETs and impacts on digital circuits