Sanghyub Lee

TL;DR: Graphene bilayer formed by aligned transfer of two single-crystalline monolayers on a wafer-scale has a well-defined interface and is electronically equivalent to exfoliated or direct-grown AB-stacked bilayers.

TL;DR: An approach for controlling the layer thickness and crystallographic stacking sequence of multilayer graphene films at the wafer scale via Cu–Si alloy formation using direct chemical vapour deposition is proposed.

TL;DR: It is demonstrated that heterointerface control is one of keys to achieving high device performance by constructing WSe2/SnSe2 heterostructures in inert gas environments and that diode behavior can be further modulated by controlling the electrostatic doping and the tunneling barrier as well.

TL;DR: It is observed, that graphene/Cu2O hybrid structures significantly slows down the oxidation compared to using a bare Cu substrate, and the thickness of the CuO layer on the bareCu substrate was increased to approximately 270 nm.

TL;DR: This work proposes a Gr/MoS2 heterojunction platform, i.e., junction field-effect transistor (JFET), that enhances the carrier mobility by a factor of ~ 10 (~ 100 cm2 V−1 s−1) compared to that of monolayer MoS2, while retaining a high on/off current ratio of‬ 108 at room temperature.