The highly scalable ferroelectric hafnia‐based thin films can be easily integrated into ferroelectric field‐effect transistors (FeFETs) by existing Si technology, which are regarded as one of the promising candidates for fast read/write, energy‐efficient, and high‐density nonvolatile memories. However, device‐to‐device variation in threshold voltage (VTH) caused by non‐uniformity of ferroelectric properties is a serious challenge for implementing hafnia‐based FeFETs in high‐density nonvolatile memories. Here, the substrate‐orientation independent growth of Hf0.5Zr0.5O2 (HZO) thin films is realized with uniform ferroelectricity by using HfO2 seed layers. The HfO2 seed layers are beneficial to improving the ferroelectric polarization of HZO thin films grown on differently oriented Si substrates and reducing the variation in ferroelectric properties. Moreover, device simulation confirms that the proposed scheme contributes to realizing uniform memory properties in 3D vertical HZO‐based FeFETs. This study suggests the possibility to implement hafnia‐based FeFETs into 3D vertical high‐density memory.

Orientation Independent Growth of Uniform Ferroelectric Hf0.5Zr0.5O2 Thin Films on Silicon for High‐Density 3D Memory Applications

We present herewith a novel approach of equally thick AFE/FE (ZrO2/HZO) bilayer stack heterostructure films for achieving an equivalent oxide thickness (EOT) of 4.1 Å with a dielectric constant (κ) of 56 in complementary metal-oxide semiconductor (CMOS) compatible metal-ferroelectric-metal (MFM) capacitors using a high-pressure annealing (HPA) technique. The low EOT and high κ values were achieved by careful optimization of AFE/FE film thicknesses and HPA conditions near the morphotropic phase boundary (MPB) after field cycling effects. Stable leakage current density (J < 10-7 A/cm2 at ±0.8 V) was found at 3/3 nm bilayer stack films (κ = 56 and EOT = 4.1 Å) measured at room temperature. In comparison with previous work, our remarkable achievement stems from the interfacial coupling between FE and AFE films as well as a high-quality crystalline structure formed by HPA. Kinetically stabilized hafnia films result in a small grain size in bilayer films, leading to reducing the leakage current density. Further, a higher κ value of 59 and lower EOT of 3.4 Å were found at 333 K. However, stable leakage current density was found at 273 K with a high κ value of 53 and EOT of 3.85 Å with J < 10-7 A/cm2. This is the lowest recorded EOT employing hafnia and TiN electrodes that are compatible with CMOS, and it has important implications for future dynamic random access memory (DRAM) technology.

Novel Approach to High κ (∼59) and Low EOT (∼3.8 Å) near the Morphotrophic Phase Boundary with AFE/FE (ZrO2/HZO) Bilayer Heterostructures and High-Pressure Annealing.

Hafnia-based ferroelectric thin-film transistors (FeTFTs) are regarded as promising candidates for future nonvolatile memory devices owing to their low power consumption, high operational speed, and complementary metal–oxide–semiconductor compatibility. However, the scalability of hafnia-based materials and the feasibility of three-dimensional (3D) device fabrication should be confirmed for ultrahigh-density memory applications. In this work, we demonstrate that FeTFTs can be scaled down to a 10-nm dimension using the vertical structure with a hafnia-based ferroelectric gate insulating layer and an oxide semiconductor channel. We show that such vertical FeTFTs can be operated with an effective device size of 0.005 μm2, a fast operation speed of <100 ns, and a high endurance of 108 cycles. Additionally, the string-level NAND operation is demonstrated using the vertical FeTFT array. Finally, device simulation confirms the possibility of ultrahigh-density 3D ferroelectric NAND with 200 gate stacks. These results demonstrate the ultrahigh scalability of FeTFTs as a promising candidate for next-generation 3D nonvolatile memory.

Vertical ferroelectric thin-film transistor array with a 10-nm gate length for high-density three-dimensional memory applications

In the present hyper-scaling era, memory technology is advancing owing to the demand for high-performance computing and storage devices. As a result, continuous work on conventional semiconductor-process-compatible ferroelectric memory devices such as ferroelectric field-effect transistors, ferroelectric random-access memory, and dynamic random-access memory (DRAM) cell capacitors is ongoing. To operate high-performance computing devices, high-density, high-speed, and reliable memory devices such as DRAMs are required. Consequently, considerable attention has been devoted to the enhanced high dielectric constant and reduced equivalent oxide thickness (EOT) of DRAM cell capacitors. The advancement of ferroelectric hafnia has enabled the development of various devices, such as ferroelectric memories, piezoelectric sensors, and energy harvesters. Therefore, in this review, we focus the morphotropic phase boundary (MPB) between ferroelectric orthorhombic and tetragonal phases, where we can achieve a high dielectric constant and thereby reduce the EOT. We also present the role of the MPB in perovskite and fluorite structures as well as the history of the MPB phase. We also address the different approaches for achieving the MPB phase in a hafnia material system. Subsequently, we review the critical issues in DRAM technology using hafnia materials. Finally, we present various applications of the hafnia material system near the MPB, such as memory, sensors, and energy harvesters. 

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A review on morphotropic phase boundary in fluorite-structure hafnia towards DRAM technology

Advances in the theory of semiconductors in the 1930s in addition to the purification of germanium and silicon crystals in the 1940s enabled the point-contact junction transistor in 1947 and initiated the era of semiconductor electronics. Gordon Moore postulated 18 years later that the number of components in an integrated circuit would double every 1 to 2 years with associated reductions in cost per transistor. Transistor density doubling through scaling—the decrease of component sizes—with each new process node continues today, albeit at a slower pace compared with historical rates of scaling. Transistor scaling has resulted in exponential gain in performance and energy efficiency of integrated circuits, which transformed computing from mainframes to personal computers and from mobile computing to cloud computing. Innovations in new materials, transistor structures, and lithographic technologies will enable further scaling. Monolithic 3D integration, design technology co-optimization, alternative switching mechanisms, and cryogenic operation could enable further transistor scaling and improved energy efficiency in the foreseeable future. Description

Toward attojoule switching energy in logic transistors

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage1. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO2 (ref. 2), which remains the material of choice to date. Here we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is equivalent to an effective SiO2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-dielectric-constant gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current3. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO2-ZrO2 multilayers, stabilized with competing ferroelectric-antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO2-based high-dielectric-constant materials. 

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Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors

Recently, hardware implementation of neuromorphic device in the optical domain is considered as one of the most promising routes to realize energy-efficient neuromorphic computing systems. Especially, a complete plasticity modulation by all-photonic stimulation has been one of the most important challenges for implementation of an optoelectronic neuromorphic device. Here, we demonstrate a fully optically driven bidirectional synaptic device using ionic electrolyte transistors. The photovoltaic divider enables wavelength-selective light-to-voltage conversion and subsequently induces ionic migration in the electrolyte, resulting in the synaptic potentiation or depression. Based on the synaptic characteristics, pattern recognition with an accuracy up to 90.1% is obtained in the Modified National Institute of Standards and Technology simulation. 

Seung-Ji Nam

Papers

Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors

Bidirectionally Modulated Synaptic Plasticity with Optically Tunable Ionic Electrolyte Transistors

Enhanced Optoelectronic Properties of Solution-Processed Metal-Chalcogenide Devices Via Hydrogen-Driven Post-Annealing