Ravi Rastogi

TL;DR: In this article, a new process, called SC1, is proposed to increase the integration scale and enhance fabrication capabilities of superconductor electronics fabrication processes, in which Nb/Al/AlO wires are placed near the bottom of the layer stack, preceded only by two planarized layers: resistor layer and superconducting ground plane.

TL;DR: In this article , a gate stack for high-dielectric-constant HfO2-ZrO2 superlattice heterostructures is presented, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms.

TL;DR: In this article, a fabrication process with self-shunted high-joints and compact thin-film kinetic inductors instead of geometrical inductors is presented.

TL;DR: In this paper, a self-shunted high-J$_c$ Josephson junctions (JJs) and compact thin-film MoN$_x$ kinetic inductors instead of geometrical inductors are presented.

TL;DR: In this article, a two-junction-layer process for superconductor electronics that integrates two layers of Josephson junctions (JJs) in a fully planarized multilayer process on 200mm wafers is presented.