Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Memristor-enabled neuromorphic computing systems provide a fast and energy-efficient approach to training neural networks1–4. However, convolutional neural networks (CNNs)—one of the most important models for image recognition5—have not yet been fully hardware-implemented using memristor crossbars, which are cross-point arrays with a memristor device at each intersection. Moreover, achieving software-comparable results is highly challenging owing to the poor yield, large variation and other non-ideal characteristics of devices6–9. Here we report the fabrication of high-yield, high-performance and uniform memristor crossbar arrays for the implementation of CNNs, which integrate eight 2,048-cell memristor arrays to improve parallel-computing efficiency. In addition, we propose an effective hybrid-training method to adapt to device imperfections and improve the overall system performance. We built a five-layer memristor-based CNN to perform MNIST10 image recognition, and achieved a high accuracy of more than 96 per cent. In addition to parallel convolutions using different kernels with shared inputs, replication of multiple identical kernels in memristor arrays was demonstrated for processing different inputs in parallel. The memristor-based CNN neuromorphic system has an energy efficiency more than two orders of magnitude greater than that of state-of-the-art graphics-processing units, and is shown to be scalable to larger networks, such as residual neural networks. Our results are expected to enable a viable memristor-based non-von Neumann hardware solution for deep neural networks and edge computing. A fully hardware-based memristor convolutional neural network using a hybrid training method achieves an energy efficiency more than two orders of magnitude greater than that of graphics-processing units.

Fully hardware-implemented memristor convolutional neural network

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators. The lack of scalable, high-quality insulators is a major problem hindering the progress on electronic devices built from 2D materials. Here, the authors review the current state-of-the-art and the future prospects of suitable insulators for 2D technologies.

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Insulators for 2D nanoelectronics: the gap to bridge.

A new method, called gate current random telegraph noise (IG RTN), was developed to analyze the oxide quality and reliability of high-k gate dielectric MOSFETs. First, a single electron trapping/detrapping from process induced trap in nMOSFET was observed and the associated physical mechanism was proposed. Secondly, IG RTN has also been successfully applied to differentiate the difference in electron tunneling mechanism for a device under high-field or low-field stress. Finally, the soft-breakdown (SBD) behavior of a device can be clearly identified. Its IG RTN characteristic is different from that before soft-breakdown. It was found that SBD will indeed induce extra leakage current as a result of an additional breakdown path.

The observation of trapping and detrapping effects in high-k gate dielectric MOSFETs by a new gate current Random Telegraph Noise (IG-RTN) approach

A new decoupled C-V method is proposed to determine the intrinsic (effective) channel region and extrinsic overlap region for miniaturized MOSFET's. In this approach, a unique channel-length-independent extrinsic overlap region is extracted at a critical gate bias, so bias-independent effective channel lengths (L/sub eff/) are achieved. Furthermore, the two-dimensional (2D) charge sharing effect is separated from the effective channel region. Based on this L/sub eff/ and the associated bias-dependent channel mobility, /spl mu//sub eff/, the drain-and-source series resistance (R/sub DS/) can be derived from the I-V characteristics for each device individually. For the first time, the assumption or approximation for R/sub DS/ and /spl mu//sub eff/ can be avoided, thus the difficulties and controversy encountered in the conventional I-V method can be solved. The 2D charge sharing effect is incorporated into the bias-dependent R/sub DS/. This bias dependence is closely related to the drain/source doping profile and the channel dopant concentration. The proposed L/sub eff/ and R/sub DS/ extraction method has been verified by an analytical I-V model which shows excellent agreements with the measured I-V characteristics. >

A new approach to determine the effective channel length and the drain-and-source series resistance of miniaturized MOSFET's

Developing high performance self-selective cell (SSC) is one of the most critical issues of the integration of 3D vertical RRAM (V-RRAM). In this work, a four-layer V-RRAM array, with high performance HfO2/mixed ionic and electronic conductor (MIEC) bilayer SSC, was demonstrated for the first time. Several salient features were achieved, including ultra-low half-select leakage ( 103), low operation current (nA level), self-compliance, high endurance (>107), and robust read/write disturbance immunity.

Demonstration of 3D vertical RRAM with ultra low-leakage, high-selectivity and self-compliance memory cells

A method for determining the intrinsic drain-and-source series resistance and the effective channel length of LDD MOSFET's is proposed. The method is based on the experimentally measured device I-V characteristics and a new parameter extraction procedure. A consistent set of the effective channel length and the gate-voltage-dependent drain-and-source series resistance was thus determined. The comparison between the measured and experimental drain current characteristics shows excellent agreement using the present model values. >

https://ir.nctu.edu.tw:443/bitstream/11536/2869/1/A1993LU39400021.pdf

A new approach to determine the drain-and-source series resistance of LDD MOSFET's

Previous studies showed that simultaneous determination of the interface states (Nit) and oxide-trapped charges (Q/sub ox/) in the vicinity of the drain side in MOS devices was rather difficult. A new technique which allows a consistent characterization of the spatial distributions of both hot-carrier-induced Nit and Q/sub ox/ is presented. Submicron LDD n-MOS devices were tested and charge pumping measurements were performed. The spatial distributions of both Nit and Q/sub ox/ have been justified by two-dimensional (2-D) device simulation of the I-V characteristics for devices before and after the stress. Comparison of the drain current characteristics between simulation and experiment shows very good agreement. Moreover, results show that fixed-oxide charge effect is less pronounced to the device degradation for the experimental LDD-type n-MOS devices.

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Steve S. Chung

Papers

The observation of trapping and detrapping effects in high-k gate dielectric MOSFETs by a new gate current Random Telegraph Noise (IG-RTN) approach

A new approach to determine the effective channel length and the drain-and-source series resistance of miniaturized MOSFET's

Demonstration of 3D vertical RRAM with ultra low-leakage, high-selectivity and self-compliance memory cells

A new approach to determine the drain-and-source series resistance of LDD MOSFET's

A new method for characterizing the spatial distributions of interface states and oxide-trapped charges in LDD n-MOSFETs