Showing papers by "Sung-min Kim published in 2005"

High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

Abstract: For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process With 10nm diameter nanowire, saturation currents through twin nanowires of 264 mA/mum, 111 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively No roll-off of threshold voltages, ~70 mV/dec of substhreshold swing (SS), and ~20 mV/V of drain induced barrier lowering(DIBL) down to 30 nm gate length are observed for both n-ch and p-ch TSNWFETs

Methods of forming a multi-bridge-channel MOSFET

Abstract: A multi-bridge-channel MOSFET (MBCFET) may be formed by forming a stacked structure on a substrate that includes channel layers and interchannel layers interposed between the channel layers. Trenches are formed by selectively etching the stacked structure. The trenches run across the stacked structure parallel to each other and separate a first stacked portion including channel patterns and interchannel patterns from second stacked portions including channel and interchannel layers remaining on both sides of the first stacked portion. First source and drain regions are grown using selective epitaxial growth. The first source and drain regions fill the trenches and connect to second source and drain regions defined by the second stacked portions. Marginal sections of the interchannel patterns of the first stacked portion are selectively exposed. Through tunnels are formed by selectively removing the interchannel patterns of the first stacked portion beginning with the exposed marginal sections. The through tunnels are surrounded by the first source and drain regions and the channel patterns. A gate is formed along with a gate dielectric layer, the gate filling the through tunnels and extending onto the first stacked portion.

Gate-all-around type of semiconductor device and method of fabricating the same

Abstract: A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that portions of the wall remain as pillars. A sacrificial layer is formed at the bottom of the opening. Then, the channel region is formed atop the sacrificial layer between the pillars. The sacrificial layer is subsequently removed and the gate oxide and gate electrode are formed around the channel region. One or more sidewall spacers are used to establish the effective width of the channel region and/or minimize parasitic capacitance between the source/drain regions and gate electrode.

Semiconductor device including a multi-channel fin field effect transistor including protruding active portions and method of fabricating the same

Abstract: In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region, a portion of the semiconductor substrate in the cell region and in the peripheral circuit region including an isolation region defining an active region, a portion of the active region protruding above an upper surface of the isolation region to define at least two active channels, a gate dielectric layer formed over the active region of the semiconductor substrate including the at least two protruding active channels, a gate electrode formed over the gate dielectric layer and the isolation region of the semiconductor substrate, and a source/drain region formed in the active region of the semiconductor substrate on either side of the gate electrode.

Semiconductor device including a multi-channel fin field effect transistor and method of fabricating the same

Abstract: In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region, a portion of the semiconductor substrate in the cell region and in the peripheral circuit region including an isolation region defining an active region, a portion of the active region protruding above an upper surface of the isolation region to define at least two active channels, a gate dielectric layer formed over the active region of the semiconductor substrate including the at least two protruding active channels, a gate electrode formed over the gate dielectric layer and the isolation region of the semiconductor substrate, and a source/drain region formed in the active region of the semiconductor substrate on either side of the gate electrode.

Semiconductor devices having field effect transistors and methods of fabricating the same

Abstract: A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.

Non-volatile memory devices including divided charge storage structures and methods of fabricating the same

Abstract: A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel region between the first and second charge storage layers, and a gate electrode on the insulating layer opposite the channel region and between inner sidewalls of the first and second charge storage layers. The gate electrode extends away from the substrate beyond the first and second charge storage layers. The device further includes second and third insulating layers extending from adjacent the inner sidewalls of the first and second charge storage layers along portions of the gate electrode beyond the first and second charge storage layers. Related methods of fabrication are also discussed.

Sub-25nm single-metal gate CMOS multi-bridge-channel MOSFET (MBCFET) for high performance and low power application

Abstract: Improving the MBCFET performance further, we have successfully fabricated single-metal-gate high-performance CMOS MBCFET with elevated flat source/drain (EF-S/D) formed by low temperature cyclic selective epitaxial growth (LTC-SEG) of Si. Due to the S/D engineering and LTC-SEG process, we could achieved the symmetric threshold voltage of 0.25V and -0.22V for TiN-gate n-channel MBCFET (nMBCFET) and p-channel MBCFET (pMBCFET), respectively. This single-metal MBCFET simultaneously satisfied the requirements of high-performance (HP) and low operating power (LOP) transistors in ITRS roadmap.

Method of fabricating a fin field effect transistor having a plurality of protruding channels

Abstract: In a method of fabricating a fin field effect transistor having a plurality of protruding channels, the fin field effect transistor is formed by forming a dummy gate pattern on a first hard mask pattern and a first insulating layer on a semiconductor substrate having an active region pattern, forming a source and drain region in a portion of the active region pattern, forming a plurality of vertically protruding channels between the source and drain region, forming a gate dielectric layer on the active region pattern having the plurality of protruding channels, and forming a gate electrode on the gate dielectric layer.

Semiconductor memory device with stacked control transistors

Abstract: In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the phase-change memory cells of each of the phase-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the phase-change memory cells.

Semiconductor device comprising multichannel fin field-effect transistor and method of manufacturing the same

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and the method of manufacturing the same SOLUTION: A semiconductor device comprises a semiconductor substrate which comprises a cell region and a peripheral circuit region and in which the cell region and the peripheral circuit region comprise an active region demarcated by an element isolation film, a portion of the active region which is projected on the surface of the element isolation film and which demarcates at least two active channels, a gate oxide film formed on the active region of the semiconductor substrate having at least two projected active channels, a gate electrode formed on the element isolation film of the gate oxide film and the semiconductor substrate, and a source and a drain formed in the active region of the semiconductor substrate of both sides of each gate electrode COPYRIGHT: (C)2006,JPO&NCIPI

Fully working high performance multi-channel field effect transistor (McFET) SRAM cell on bulk Si substrate using TiN single metal gate

Abstract: We demonstrate for the first time high performance titanium nitride (TiN) single metal gate 65nm CMOS McFET (multichannel field effect transistor) SRAM cell transistor on bulk Si wafer. This single metal gate McFET shows suitable threshold voltage (VT) and excellent transistor characteristics of SS (sub-threshold swing) and DIBL (drain induced barrier lowering) with V/sub TN/ =+0.3V and V/sub TP/=-0.3V. The SRAM cell with this CMOS McFET, high static noise margin (SNM) of 350mV is achieved at 1.0V.

Lateral integration of partially insulated and bulk MOSFETs using partial SOI process

Abstract: We proposed and successfully demonstrated partially insulated and bulk MOSFETs with multiple V/sub th/s, I/sub on/s, and I/sub Off/s by using partial SOI process without complex process and SOI wafer. Both nMOS and pMOS applicable to the HP and LSTP transistors were simultaneously implemented on the same wafer with the same process except partial SOI process. These results must be very useful to implement IC systems requiring various specifications of V/sub TH/s, I/sub On/s, and I/sub Off/s.

Semiconductor device having a multi-bridge-channel and method for fabricating the same

Abstract: In a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, the device includes first and second semiconductor posts protruding from a surface of a semiconductor substrate and having a source and a drain region, respectively, in upper side portions thereof, channel semiconductor layers connecting upper side portions of the first and second semiconductor posts, a gate insulation layer on the channel semiconductor layers and the semiconductor substrate, the gate insulation layer surrounding at least a portion of the channel semiconductor layers, a gate electrode layer on the gate insulation layer to enclose at least a portion of a region between the channel semiconductor layers, and junction auxiliary layers formed between the channel semiconductor layers, the junction auxiliary layers contacting the gate electrode layer and upper side portions of the first and second semiconductor posts, and having a same width as the channel semiconductor layers.

Field effect transistor comprises wire channels electrically connecting source and drain regions and arranged in two columns and at least two rows

Abstract: A field effect transistor (FET) comprises semiconductor substrate; source and drain regions (42) formed on substrate; wire channels (12e) electrically connecting the source and drain regions and arranged in two columns and at least two rows; and gate dielectric layer surrounding each of the wire channels and a gate electrode surrounding the gate dielectric layer and each of the wire channels. An independent claim is also included for a method of fabricating a field effect transistor comprising: (a) forming a channel forming preparation layer on the semiconductor substrate, the channel forming preparation layer including a first sacrificial layer, first channel layer, second sacrificial layer and second channel layer sequentially stacked on the substrate; (b) forming a hard mask layer on the channel forming preparation layer; (c) patterning the hard mask layer and the channel forming preparation layer to define an active region of the substrate; (d) patterning the hard mask layer to narrow the hard mask layer exposing an edge portion of an upper surface of the channel forming preparation layer; (e) forming a first dielectric layer on the substrate to cover the narrowed hard mask layer and the channel forming preparation layer, then planarizing the first dielectric layer to expose the narrowed hard mask layer; (f) patterning the first dielectric layer and a portion of the narrowed hard mask layer to remove a portion of the narrowed hard mask layer to form a dummy gate pattern and exposing a portion of the channel forming preparation layer; (g) selectively etching the exposed portion of the channel forming preparation layer adjacent to the dummy gate pattern to expose the substrate; (h) selectively growing an epitaxial layer on the exposed substrate to form source and drain patterns (40) adjacent to the channel forming preparation layer; (i) forming a second dielectric layer on the substrate including the dummy gate and the source and drain patterns and then planarizing the second dielectric layer to expose the dummy gate pattern; (j) selectively etching the remaining hard mask layer to remove the remaining hard mask layer so exposing a portion of the channel forming preparation layer and then etching the exposed portion of the channel forming preparation layer to expose the substrate; (k) removing the second dielectric layer and an upper portion of the first dielectric layer to expose sidewalls of the channel forming preparation layer remaining on the substrate; (l) selectively etching the channel forming preparation layer to remove the two sacrificial layers to form wire channels from the two channel layers; (m) forming a gate dielectric layer on the substrate to surround each of the wire channels; and (n) forming a gate electrode on the gate dielectric layer to form a gate surrounding each of the wire channels.

Methods of fabricating non-volatile memory devices including divided charge storage structures

Abstract: A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel region between the first and second charge storage layers, and a gate electrode on the insulating layer opposite the channel region and between inner sidewalls of the first and second charge storage layers. The gate electrode extends away from the substrate beyond the first and second charge storage layers. The device further includes second and third insulating layers extending from adjacent the inner sidewalls of the first and second charge storage layers along portions of the gate electrode beyond the first and second charge storage layers. Related methods of fabrication are also discussed.

Single-metal gate multi-bridge-channel MOSFET (MBCFET) for CMOS application

Abstract: Simplifying the MBCFET process further, the authors have successfully fabricated single-metal-gate CMOS MBCFET. Due to channel engineering, the symmetric threshold voltage of 0.25V and -0.22V for single TiN-gate n-channel MBCFET (nMBCFET) and p-channel MBCFET (pMBCFET), could be achieved respectively.