S
Sungjae Lee
Researcher at IBM
Publications - 17
Citations - 525
Sungjae Lee is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Field-effect transistor. The author has an hindex of 10, co-authored 17 publications receiving 499 citations.
Papers
More filters
Proceedings ArticleDOI
Record RF performance of 45-nm SOI CMOS Technology
Sungjae Lee,Basanth Jagannathan,Shreesh Narasimha,Anthony I. Chou,Noah Zamdmer,J. Johnson,Richard Q. Williams,Lawrence F. Wagner,Jonghae Kim,Jean-Olivier Plouchart,John J. Pekarik,Scott K. Springer,Gregory G. Freeman +12 more
TL;DR: In this article, the authors report record RF performance in 45-nm silicon-on-insulator (SOI) CMOS technology and demonstrate that RF performance scaling with channel length and layout optimization is demonstrated.
Journal ArticleDOI
Modeling of Variation in Submicrometer CMOS ULSI Technologies
Scott K. Springer,Sungjae Lee,Ning Lu,E. J. Nowak,Jean-Olivier Plouchart,Josef S. Watts,Richard Q. Williams,Noah Zamdmer +7 more
TL;DR: In this paper, the authors present the challenges and results of compact modeling at the 65-nm node and beyond, as well as the modeling of intradie and interdie variations, updated for small geometries.
Proceedings ArticleDOI
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond
Ali Khakifirooz,Kangguo Cheng,Basanth Jagannathan,Pranita Kulkarni,Jeffrey W. Sleight,Davood Shahrjerdi,Josephine B. Chang,Sungjae Lee,Junjun Li,Huiming Bu,Robert J. Gauthier,Bruce B. Doris,Ghavam G. Shahidi +12 more
TL;DR: Extremely thin SOI (ETSOI) MOSFET is an attractive candidate for 22nm technology and beyond due to its excellent short channel control, low leakage current, and immunity to random dopant fluctuation.
Proceedings ArticleDOI
Record RF performance of sub-46 nm L/sub gate/ NFETs in microprocessor SOI CMOS technologies
Sungjae Lee,Lawrence F. Wagner,Basanth Jagannathan,Sebastian Csutak,John J. Pekarik,Matthew J. Breitwisch,R. Ramachandran,Gregory G. Freeman +7 more
TL;DR: In this article, the effect of layout and geometry optimization as well as channel length scaling is investigated to improve RF performance, namely fT, and fMAX, in 65 and 90-nm silicon-on-insulator (SOI) CMOS technologies featuring measured gate lengths from 27 to 43 nm.
Proceedings Article
Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices
Sungjae Lee,Richard A. Wachnik,Paul A. Hyde,Lawrence F. Wagner,J. Johnson,Anthony I. Chou,Amit Kumar,Shreesh Narasimha,Theodorus E. Standaert,Brian J. Greene,Tenko Yamashita,Karthik Balakrishnan,Huiming Bu,Scott K. Springer,Gregory G. Freeman,William K. Henson,E. J. Nowak +16 more
TL;DR: In this article, a quantitative comparison of planar and FinFET devices on dielectric isolation has been conducted, and it has been shown that planar devices exhibit higher normalized thermal resistance, as expected from device scaling, while the characteristic time constant for self heating is still well below the operating frequency of typical logic circuits.