From the Publisher: 
The accessible presentation of this book gives both a general view of the entire computer vision enterprise and also offers sufficient detail to be able to build useful applications. Users learn techniques that have proven to be useful by first-hand experience and a wide range of mathematical methods. A CD-ROM with every copy of the text contains source code for programming practice, color images, and illustrative movies. Comprehensive and up-to-date, this book includes essential topics that either reflect practical significance or are of theoretical importance. Topics are discussed in substantial and increasing depth. Application surveys describe numerous important application areas such as image based rendering and digital libraries. Many important algorithms broken down and illustrated in pseudo code. Appropriate for use by engineers as a comprehensive reference to the computer vision enterprise.

Computer vision : a modern approach = 计算机视觉 : 一种现代的方法

An overview of the self-organizing map algorithm, on which the papers in this issue are based, is presented in this article.

The Self-Organizing Map

Fast Fourier Transform

Computer algebra systems are now ubiquitous in all areas of science and engineering. This highly successful textbook, widely regarded as the “bible of computer algebra”, gives a thorough introduction to the algorithmic basis of the mathematical engine in computer algebra systems. Designed to accompany oneor two-semester courses for advanced undergraduate or graduate students in computer science or mathematics, its comprehensiveness and reliability has also made it an essential reference for professionals in the area. Special features include: detailed study of algorithms including time analysis; implementation reports on several topics; complete proofs of the mathematical underpinnings; and a wide variety of applications (among others, in chemistry, coding theory, cryptography, computational logic, and the design of calendars and musical scales). A great deal of historical information and illustration enlivens the text. In this third edition, errors have been corrected and much of the Fast Euclidean Algorithm chapter has been renovated.

Modern computer algebra

The Artificial Intelligence field continues to be plagued by what can only be described as ‘bold promises for the future syndrome’, often perpetrated by researchers who should know better. While impartial assessment can point to concrete contributions over the past 50 years (such as automated theorem proving, games strategies, the LISP and Prolog high-level computer languages, Automatic Speech Recognition, Natural Language Processing, mobile robot path planning, unmanned vehicles, humanoid robots, data mining, and more), the more cynical argue that AI has witnessed more than its fair share of ‘unmitigated disasters’ during this time – see, for example [3,58,107,125,186]. The general public becomes rapidly jaded with such ‘bold predictions’ that fail to live up to their original hype, and which ultimately render the zealots’ promises as counter-productive.

Computational Intelligence: An Introduction

In this paper, we present the prototypical implementation of the scalable GigaNetIC chip multiprocessor architecture. We use an FPGA-based rapid prototyping system to verify the functionality of our architecture in a network application scenario before we are going to fabricate the ASIC in a modern CMOS standard cell technology. The rapid prototyping environment gives us the opportunity to test our multiprocessor architecture with Ethernet-based data streams in a real network scenario. Our system concept is based on a massively parallel processor structure. Due to its regularity, our architecture can be easily scaled to accommodate a wide range of packet processing applications with disparate performance and throughput requirements at high reliability. Furthermore, the composition from predefined building blocks guarantees fast design cycles and simplifies system verification. We present standard cell synthesis results as well as a performance analysis for a firewall application with various couplings of hardware accelerators.

GigaNetIC – a scalable embedded on-chip multiprocessor architecture for network applications

In this work we discuss the resource efficiency of scalable processor architectures for software-defined radio (SDR) based applications. The development of resource efficient processor architectures is based on a two-staged design flow using a high level processor specification as a reference. This design-flow has been used to perform a comprehensive design-space exploration of algorithms from various application scenarios. As a result the 4-issue VLIWarchitecture CoreVA has been implemented. The finegrained parallelism of this architecture allows for performance gains of up to a factor of three to four for the analyzed application scenarios. From the design-space exploration on system level dedicated hardware accelerators have been derived. The hardware accelerators proposed in this work improve the energy efficiency by a factor of 6 to 43. To further improve the performance of the system, the single-core based approach is extended to network-on-chip (NoC) level. As an example, an IEEE 802.11b application has been mapped to a cluster of four processor cores reducing the processing time of the algorithm by up to 60 %.

Resource Efficiency of Scalable Processor Architectures for SDR-based Applications (Invited)

In this paper a hardware extension for the minirobot Khepera is presented We are researching into algorithms for neural data processing and their hardware implementation by increasingly using the minirobot Khepera This robot is supposed to record its environment continuously and to map obstacles This is the basis for the implementation of an efficient navigational system As the algorithms in question are complex and since the microcontroller on the Khepera does not possess the necessary processing capacity, it is requisite to develop a discrete hardware module that extends the Khepera

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Extension Module for Application-Specific Hardware on the Minirobot Khepera

FPGA-based Generic Architecture for Rapid Prototyping of Video Hardware Accelerators using NoC AXI4-Stream Interconnect and GigE Vision Camera Interfaces

This paper presents an extension turret for efficient data processing for autonomous minirobots, in particular the minirobot Khepera. The Khepera robot is a base platform of a mobile autonomous system for our experiments, but the robot’s main processor cannot accomplish complex processing tasks with real-time requirements, because of the processor’s low performance. Thus, we have designed an extension hardware module based on a field programmable gate array (FPGA) to run the real-time processing and concurrently control other peripheral modules. The module with coupling of FPGA and a microcontroller gains robot’s ability and possesses FPGA’ flexibility of reconfiguration.

Ulrich Rückert

Papers

GigaNetIC – a scalable embedded on-chip multiprocessor architecture for network applications

Resource Efficiency of Scalable Processor Architectures for SDR-based Applications (Invited)

Extension Module for Application-Specific Hardware on the Minirobot Khepera

FPGA-based Generic Architecture for Rapid Prototyping of Video Hardware Accelerators using NoC AXI4-Stream Interconnect and GigE Vision Camera Interfaces

Universal FPGA-Microcontroller Module for Autonomous Minirobots