From the Publisher: 
The accessible presentation of this book gives both a general view of the entire computer vision enterprise and also offers sufficient detail to be able to build useful applications. Users learn techniques that have proven to be useful by first-hand experience and a wide range of mathematical methods. A CD-ROM with every copy of the text contains source code for programming practice, color images, and illustrative movies. Comprehensive and up-to-date, this book includes essential topics that either reflect practical significance or are of theoretical importance. Topics are discussed in substantial and increasing depth. Application surveys describe numerous important application areas such as image based rendering and digital libraries. Many important algorithms broken down and illustrated in pseudo code. Appropriate for use by engineers as a comprehensive reference to the computer vision enterprise.

Computer vision : a modern approach = 计算机视觉 : 一种现代的方法

An overview of the self-organizing map algorithm, on which the papers in this issue are based, is presented in this article.

The Self-Organizing Map

Fast Fourier Transform

Computer algebra systems are now ubiquitous in all areas of science and engineering. This highly successful textbook, widely regarded as the “bible of computer algebra”, gives a thorough introduction to the algorithmic basis of the mathematical engine in computer algebra systems. Designed to accompany oneor two-semester courses for advanced undergraduate or graduate students in computer science or mathematics, its comprehensiveness and reliability has also made it an essential reference for professionals in the area. Special features include: detailed study of algorithms including time analysis; implementation reports on several topics; complete proofs of the mathematical underpinnings; and a wide variety of applications (among others, in chemistry, coding theory, cryptography, computational logic, and the design of calendars and musical scales). A great deal of historical information and illustration enlivens the text. In this third edition, errors have been corrected and much of the Fast Euclidean Algorithm chapter has been renovated.

Modern computer algebra

The Artificial Intelligence field continues to be plagued by what can only be described as ‘bold promises for the future syndrome’, often perpetrated by researchers who should know better. While impartial assessment can point to concrete contributions over the past 50 years (such as automated theorem proving, games strategies, the LISP and Prolog high-level computer languages, Automatic Speech Recognition, Natural Language Processing, mobile robot path planning, unmanned vehicles, humanoid robots, data mining, and more), the more cynical argue that AI has witnessed more than its fair share of ‘unmitigated disasters’ during this time – see, for example [3,58,107,125,186]. The general public becomes rapidly jaded with such ‘bold predictions’ that fail to live up to their original hype, and which ultimately render the zealots’ promises as counter-productive.

Computational Intelligence: An Introduction

Selforganizing Feature Maps (SOFMs) can be applied for data analysis, controlling problems and pattern matching. In many cases the requirements of a system using these maps are high performance and small physical size. This leads to the necessity of custom chip designs. In this paper two chips are presented, that realize a scalable processor array for self-organizing feature maps. First the design and test results of a single processor chip are described. Based on these results a second chip has been developed implementing a 5 by 5 array of elements. Each processor has on-chip memory to store 64 weights of 8 bit. The calculation unit has an internal precision of 14 bit. An input pattern can have 64 vector components of 8 bit. In order to achieve high speed, all elements work in parallel. Several of this chips can be cascaded to larger map sizes in a system.

A scalable processor array for self-organizing feature maps

A mixed mode digital/analog special purpose VLSI hardware implementation of an associative memory with neural architecture is presented. The memory concept is based on a matrix architecture with binary storage elements holding the connection weights. To enhance the processing speed analog circuit techniques are applied to implement the algorithm for the association. To keep the memory density as high as possible two design strategies are considered. First, the number of transistors per storage element is kept to a minimum. In this paper a circuit technique that uses a single 6-transistor cell for weight storage and analog signal processing is proposed. Second, the device precision has been chosen to a moderate level to save area as much as possible. Since device mismatch limits the performance of analog circuits, the impact of device precision on the circuit performance is explicitly discussed. It is shown that the device precision limits the number of rows activated in parallel. Since the input vector as well as the output vector are considered to be sparsely coded it is concluded, that even for large matrices the proposed circuit technique is appropriate and ultra large scale integration with a large number of connection weights is feasible.

Mixed Mode VLSI Implementation of a Neural Associative Memory

In this paper we present a method to predict cognitive workload during the interaction with a tablet computer. To set up a predictor that estimates the reflected self-reported cognitive workload we analyzed the information gain of heart rate, electrodermal activity and user input (touch) based features. From the derived optimal feature set we present a Gaussian Process based learner that enables fine-grained and short term detection of cognitive workload. Average inter-subject accuracy in 10-fold cross validation is 74.1 % for the fine-grained 5-class problem and 96.0 % for the binary class problem.

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Fine-Grained Prediction of Cognitive Workload in a Modern Working Environment by Utilizing Short-Term Physiological Parameters

Experiments are essential ingredients of science to compare, validate or refute theories, methodologies, hypotheses and approaches. However, in robotics, the comparison of methods using experiments is difficult because of the variety of robotic platforms and experiment environments.
In this paper we describe the Teleworkbench and discuss the role it can take on the quest of creating repeatable and reproducible experiments in robot navigation, obtaining com- parable results as well as evaluating and analysing results. The Teleworkbench can control up to 64 mini-robots simultaneously, log user defined quantities for post-experiment analysis and monitor the experiments via cameras mounted in the ceiling. A web interface makes the Teleworkbench accessible for remotely located users. Thus, the Teleworkbench is a platform that robotic scientists can use in order to evaluate the developed approaches quantitatively and qualitatively as well as to com- pare their methods amongst each other.

The Teleworkbench: A Platform for Performing and Comparing Experiments in Robot Navigation

In this work a new FPGA based hardware accelerator (gNBX) for self-organizing maps is introduced. New principles for hardware acceleration of self-organizing maps, which increase the degree of parallelity and therefore the acceleration gain was presented. Our technology independent design description can be mapped on application specific integrated circuits if very high performance is required, as well as on field programmable gate arrays (FPGAs), which offer mid level performance (a speed up factor of up to 70 in comparison with PCs for typical datasets is achieved) at relatively low costs. Additionally, FPGAs offer the flexibility to adapt the hardware to the changing requirements of the application during runtime. Therefore, the hardware can be exploited optimally at all times during the simulation process. Several benchmark scenarios with well known datasets shows the performance of our system.

Ulrich Rückert

Papers

A scalable processor array for self-organizing feature maps

Mixed Mode VLSI Implementation of a Neural Associative Memory

Fine-Grained Prediction of Cognitive Workload in a Modern Working Environment by Utilizing Short-Term Physiological Parameters

The Teleworkbench: A Platform for Performing and Comparing Experiments in Robot Navigation

gNBX - reconfigurable hardware acceleration of self-organizing maps