From the Publisher: 
The accessible presentation of this book gives both a general view of the entire computer vision enterprise and also offers sufficient detail to be able to build useful applications. Users learn techniques that have proven to be useful by first-hand experience and a wide range of mathematical methods. A CD-ROM with every copy of the text contains source code for programming practice, color images, and illustrative movies. Comprehensive and up-to-date, this book includes essential topics that either reflect practical significance or are of theoretical importance. Topics are discussed in substantial and increasing depth. Application surveys describe numerous important application areas such as image based rendering and digital libraries. Many important algorithms broken down and illustrated in pseudo code. Appropriate for use by engineers as a comprehensive reference to the computer vision enterprise.

Computer vision : a modern approach = 计算机视觉 : 一种现代的方法

An overview of the self-organizing map algorithm, on which the papers in this issue are based, is presented in this article.

The Self-Organizing Map

Fast Fourier Transform

Computer algebra systems are now ubiquitous in all areas of science and engineering. This highly successful textbook, widely regarded as the “bible of computer algebra”, gives a thorough introduction to the algorithmic basis of the mathematical engine in computer algebra systems. Designed to accompany oneor two-semester courses for advanced undergraduate or graduate students in computer science or mathematics, its comprehensiveness and reliability has also made it an essential reference for professionals in the area. Special features include: detailed study of algorithms including time analysis; implementation reports on several topics; complete proofs of the mathematical underpinnings; and a wide variety of applications (among others, in chemistry, coding theory, cryptography, computational logic, and the design of calendars and musical scales). A great deal of historical information and illustration enlivens the text. In this third edition, errors have been corrected and much of the Fast Euclidean Algorithm chapter has been renovated.

Modern computer algebra

The Artificial Intelligence field continues to be plagued by what can only be described as ‘bold promises for the future syndrome’, often perpetrated by researchers who should know better. While impartial assessment can point to concrete contributions over the past 50 years (such as automated theorem proving, games strategies, the LISP and Prolog high-level computer languages, Automatic Speech Recognition, Natural Language Processing, mobile robot path planning, unmanned vehicles, humanoid robots, data mining, and more), the more cynical argue that AI has witnessed more than its fair share of ‘unmitigated disasters’ during this time – see, for example [3,58,107,125,186]. The general public becomes rapidly jaded with such ‘bold predictions’ that fail to live up to their original hype, and which ultimately render the zealots’ promises as counter-productive.

Computational Intelligence: An Introduction

Today's deep submicron fabrication technologies enable design engineers to put an impressive number of components like microprocessors, memories, and interfaces on a single microchip. With the emergence of 100 nm processes, billions of transistors can be integrated on one die and form a parallel system, consisting of thousands of components. To handle this impressive number of components, it is important to provide a communication infrastructure which is able to scale with the capabilities of upcoming fabrication technologies and which provides the foundation for efficient on-chip communication protocols. This paper addresses the architectural requirements which are coupled with the transfer of well known techniques from parallel computers onto the design of SoCs and proposes an on-chip architecture which is based on active switch boxes. We show that this architecture is able to fill the existing design gap between an efficient use of the design space and the design complexity, with reasonable resource requirements.

On-chip interconnects for next generation system-on-chips

In this paper, an implementation of a RISC processor core for SoC designs is presented. We analyze
the differences between a prototypical FPGA implementation and standard cell realizations
in an 0.6μm and an 0.13μm technology, respectively. The core was developed by using
the hardware description language VHDL, which offers the opportunity of adding special, optimized
hardware blocks for various operations. The effects on area and power consumption as
well as computational power are analyzed. A detailed overview of the implementation of additional
hardware multipliers and their effects on the above mentioned topics concludes this paper.

Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation

Low-power Wireless Sensor Networks (WSN) are used in various energy constraint applications in industry, medicine, and human motion monitoring. In this paper we analyze the transmission performance of a WSN in a static indoor test setup consisting of 5 to 14 transmitters and up to four receivers. In particular, we consider the nRF24L01 transceiver that implements the proprietary ANT protocol and operates in the 2.4 GHz ISM band. We conduct tests in over 500 configurations with different message frequencies, packet sizes and number of transmitters. Our tests experimentally point out the tradeoff between rate and package length regarding the number of lost packets. Moreover, we show that using multiple receivers reduces the amount of consecutively lost packages. The obtained results provide valuable insights for drawing conclusions for an application specific device configuration as well as redundancy mechanisms for maximizing the information throughput.

Ulrich Rückert

Papers

On-chip interconnects for next generation system-on-chips

Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation

On-chip interconnects for next generation system-on-chips

Performance analysis of the nRF24L01 ultra-low-power transceiver in a multi-transmitter and multi-receiver scenario

Advances in Robotics