From the Publisher: 
The accessible presentation of this book gives both a general view of the entire computer vision enterprise and also offers sufficient detail to be able to build useful applications. Users learn techniques that have proven to be useful by first-hand experience and a wide range of mathematical methods. A CD-ROM with every copy of the text contains source code for programming practice, color images, and illustrative movies. Comprehensive and up-to-date, this book includes essential topics that either reflect practical significance or are of theoretical importance. Topics are discussed in substantial and increasing depth. Application surveys describe numerous important application areas such as image based rendering and digital libraries. Many important algorithms broken down and illustrated in pseudo code. Appropriate for use by engineers as a comprehensive reference to the computer vision enterprise.

Computer vision : a modern approach = 计算机视觉 : 一种现代的方法

An overview of the self-organizing map algorithm, on which the papers in this issue are based, is presented in this article.

The Self-Organizing Map

Fast Fourier Transform

Computer algebra systems are now ubiquitous in all areas of science and engineering. This highly successful textbook, widely regarded as the “bible of computer algebra”, gives a thorough introduction to the algorithmic basis of the mathematical engine in computer algebra systems. Designed to accompany oneor two-semester courses for advanced undergraduate or graduate students in computer science or mathematics, its comprehensiveness and reliability has also made it an essential reference for professionals in the area. Special features include: detailed study of algorithms including time analysis; implementation reports on several topics; complete proofs of the mathematical underpinnings; and a wide variety of applications (among others, in chemistry, coding theory, cryptography, computational logic, and the design of calendars and musical scales). A great deal of historical information and illustration enlivens the text. In this third edition, errors have been corrected and much of the Fast Euclidean Algorithm chapter has been renovated.

Modern computer algebra

The Artificial Intelligence field continues to be plagued by what can only be described as ‘bold promises for the future syndrome’, often perpetrated by researchers who should know better. While impartial assessment can point to concrete contributions over the past 50 years (such as automated theorem proving, games strategies, the LISP and Prolog high-level computer languages, Automatic Speech Recognition, Natural Language Processing, mobile robot path planning, unmanned vehicles, humanoid robots, data mining, and more), the more cynical argue that AI has witnessed more than its fair share of ‘unmitigated disasters’ during this time – see, for example [3,58,107,125,186]. The general public becomes rapidly jaded with such ‘bold predictions’ that fail to live up to their original hype, and which ultimately render the zealots’ promises as counter-productive.

Computational Intelligence: An Introduction

Communication facilities are important in Robotics if several robots have to work together. In this paper, we describe problems and solutions encountered while de- signing an infrared-based communication device for the mini robot Khepera. In contrast to traditional omnidirectional systems, it features directed, power-variable transmission in eight directions at 23.4 kbps up to a range of 1m . It can differentiate incoming data sig- nals from interference from adjacent sectors and can estimate their direction-of-arrival. We model the transmission over the infrared channel and show how interference influences the reception of the data signals. We also describe methods how to reduce these effects. We have tested the performance of the resulted signal processing in a worst case scenario by simulations and in experiments with a prototype implementation. The resulted module is especially suited for experimental evaluation of ad hoc network protocols and for position estimation.

Directed power-variable infrared communication for the mini robot Khepera

Using a Dynamically Reconfigurable System to Accelerate Octree Based 3D Graphics

Resource efficiency of the GigaNetIC chip multiprocessor architecture

Embedded many-core architectures contain dozens to hundreds of CPU cores that are connected via a highly scalable NoC interconnect. Our Multiprocessor-System-on-Chip CoreVA-MPSoC combines the advantages of tightly coupled bus-based communication with the scalability of NoC approaches by adding a CPU cluster as an additional level of hierarchy. In this work, we analyze different cluster interconnect implementations with 8 to 32 CPUs and compare them in terms of resource requirements and performance to hierarchical NoCs approaches. Using 28 nm FD-SOI technology the area requirement for 32 CPUs and AXI crossbar is 5.59 mm2 including 23.61% for the interconnect at a clock frequency of 830 MHz. In comparison, a hierarchical MPSoC with 4 CPU cluster and 8 CPUs in each cluster requires only 4.83 mm2 including 11.61% for the interconnect. To evaluate the performance, we use a compiler for streaming applications to map programs to the different MPSoC configurations. We use this approach for a design-space exploration to find the most efficient architecture and partitioning for an application.

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Evaluation of interconnect fabrics for an embedded MPSoC in 28 nm FD-SOI

A number of applications of self organizing feature maps require a powerful hardware. The algorithm of SOFMs contains multiplications, which need a large chip area for fast implementation in hardware. In this paper a resticted class of self organizing feature maps is investigated. Hardware aspects are the fundamental ideas for the restictions, so that the necessary chip area for each processor element in the map can be much smaller then before and more elements per chip can work in parallel. Binary input vectors, Manhatten Distance and a special treatment of the adaptation factor allow an efficient implementation. A hardware design using this algorithm is presented. VHDL simulations show a performance of 25600 MCPS (Million Connections Per Second) during the recall phase and 1500 MCUPS (Million Connections Updates Per Second) during the learning phase for a 50 by 50 map. A first standard cell layout containing 16 processor elements and full custom designs for the most important parts are presented.

Ulrich Rückert

Papers

Directed power-variable infrared communication for the mini robot Khepera

Using a Dynamically Reconfigurable System to Accelerate Octree Based 3D Graphics

Resource efficiency of the GigaNetIC chip multiprocessor architecture

Evaluation of interconnect fabrics for an embedded MPSoC in 28 nm FD-SOI

Hardware Design for Self-Organizing Feature Maps with Binary Input Vectors