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Ulrich Rückert

Researcher at Bielefeld University

Publications -  363
Citations -  3446

Ulrich Rückert is an academic researcher from Bielefeld University. The author has contributed to research in topics: Robot & Field-programmable gate array. The author has an hindex of 26, co-authored 357 publications receiving 3235 citations. Previous affiliations of Ulrich Rückert include Technische Universität München & Technical University of Dortmund.

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Proceedings ArticleDOI

Bio-inspired massively parallel architectures for nanotechnologies

TL;DR: A first comparison of CMPs based on processor cores of different complexity is presented and the efficiency of C MPs with regards to overall performance and energy consumption is estimated.
Patent

Meta-information managing method for distributing data blocks or objects over computer-readable storage media, especially in fault-tolerant systems, combines extent and offset fraction for uniform data distribution

TL;DR: In this paper, the authors propose a method to store data in extents whose addresses are distributed uniformly over the storage media by use of an address bit fraction and an offset bit fraction, where the addressing jumps the storage location no longer required for storing the extents coherently within consecutive ranges on a memory unit within the memory system.

Performance Analysis of a Colony of Locally Communicating Robots

TL;DR: The performance of the robot colony solving the cube clustering problem is analysed regarding the number of cluster points and the optimal robot density that solves the problem the fastest.
Proceedings ArticleDOI

European “synQPSK” Project: Toward Synchronous Optical Quadrature Phase Shift Keying with DFB Lasers

TL;DR: Key components for a synchronous 10-Gbaud, 40-Gbit/s QPSK polarization division multiplex transmission testbed are being developed: LiNbO3 Z-cut QPSk modulator, LiN bO3 90° hybrid co-packaged with balanced photoreceiver OEICs, SiGe/CMOS circuits for digital signal processing.
Proceedings ArticleDOI

An analog local cluster neural net for a 3 V supply

TL;DR: The CMOS VLSI realization of the local cluster neural net is described and the results of the comprehensive test measurement for characterising the performance of the implementation are presented.