Showing papers by "Veena Misra published in 1999"

Bonding constraints and defect formation at interfaces between crystalline silicon and advanced single layer and composite gate dielectrics

Abstract: An increasingly important issue in semiconductor device physics is understanding of how departures from ideal bonding at silicon–dielectric interfaces generate electrically active defects that limit performance and reliability Building on previously established criteria for formation of low defect density glasses, constraint theory is extended to crystalline silicon–dielectric interfaces that go beyond Si–SiO2 through development of a model that quantifies average bonding coordination at these interfaces This extension is validated by application to interfaces between Si and stacked silicon oxide/nitride dielectrics demonstrating that as in bulk glasses and thin films, an average coordination, Nav, greater than three yields increasing defective interfaces

Interfacial properties of ultrathin pure silicon nitride formed by remote plasma enhanced chemical vapor deposition

Abstract: This article addresses the electrical properties of interfaces between n- and p-type Si and remote plasma-deposited Si3N4, which are of interest in aggressively scaled advanced CMOSFETs. The nitride films of this article display excellent electrical properties when implemented into stacked oxide/nitride dielectrics in both NMOSFETs and PMOSFETs with oxide, or nitrided oxide interfaces. The same nitride layers deposited directly onto clean Si surfaces display degraded electrical properties with respect to devices with oxide, or nitrided oxide interfaces. PMOS interfaces are significantly more degraded than n-type metal–oxide semiconductors interfaces indicating a relatively high density of donor-like interface traps that inhibit channel formation.

Bonding constraint-induced defect formation at Si-dielectric interfaces and internal interfaces in dual-layer gate dielectrics

Abstract: As aggressive scaling of integrated circuits continues into the next century, insulators with dielectric constants higher than SiO2 with different local bonding arrangements will be required to increase gate dielectric capacitance in field effect transistor devices. An important issue in semiconductor device physics is determining whether differences between the bonding at (i) Si–SiO2 interfaces and (ii) interfaces between crystalline Si and alternative gate dielectric materials will result in increased densities of electrically active defects at the alternative dielectric interfaces, thereby limiting targeted levels of performance and reliability. In particular, it is important to understand from a chemical bonding perspective why Si–SiO2 interfaces display both low defect densities and high reliability, while other interfaces such as Si–Si3N4 with similar bonding chemistry, display defect densities that are at least two orders of magnitude higher. Building on previously established criteria for formatio...

Interfacial Properties of Si−Si3N4formed by Remote Plasma Enhanced Chemical Vapor Deposition

Abstract: This paper presents results on the interfacial properties of Si3N4on NMOSFETs and PMOSFETs. Silicon nitride, formed by remote plasma enhanced chemical vapor deposition, was found to display severely degraded interfacial properties, in which the PMOS interfaces were significantly more degraded than NMOS interfaces. This is believed to be indicative of a relatively high density of interface traps located below the Si mid-gap that inhibit hole channel formation. These traps are believed to originate from the intrinsic nature of Si- Si3N4interface. Bonding constraint theory was applied to conclude that the Si-Si3N4interface is over-constrained compared to the Si-SiO2interface and consequently results in a higher intrinsic defectivity. A systematic study of the oxygen and hydrogen content in the silicon nitride film and its effect on electrical properties is also presented. Based on the electrical results it is concluded that the presence of oxygen either as a) a monolayer at the interface or b) within the silicon nitride film can produce high quality interfaces suitable for aggressively scaled CMOS devices.

A Low‐Thermal‐Budget In Situ Doped Multilayer Silicon Epitaxy Process for MOSFET Channel Engineering

Abstract: This paper describes an in situ boron‐doped, multilayer epitaxial silicon process that can be used to obtain doping profiles for channels in the deep‐submicron regime. We have extensively studied lightly doped channel structures in which an intrinsic silicon layer is grown on an in situ doped epitaxial silicon film. Low‐thermal‐budget processing is achieved by the ultrahigh‐vacuum rapid thermal chemical vapor deposition technique which combines low‐temperature surface preparation and deposition (≤800°C) while providing high growth rates using disilane . Boron doping is achieved using diborane diluted in hydrogen (500 ppm) as the precursor. Temperature and gas switching are compared in terms of doping transition, interface contamination (carbon and oxygen incorporation), and impurity diffusion upon annealing. Our results reveal that for a contamination‐free epitaxial silicon interface, interfacial carbon contamination must be eliminated or reduced to a minimum level. Using this process, short‐channel n‐channel metal‐oxide semiconductor devices μm) have been fabricated for the first time demonstrating the potential use of the technique. It was found that lightly doped channel metal‐oxide semiconductor field effect transistors are more easily scalable into the 0.1 μm regime with superior short‐channel characteristics. © 1999 The Electrochemical Society. All rights reserved.