The remarkable growth of wireless data traffic in recent times has driven the need to explore suitable regions in the radio spectrum to meet the projected requirements. In pursuance of this, millimeter wave communications have received considerable attention in the research fraternity. Due to the high path and penetration losses at millimeter wavelengths, antenna beamforming assumes a pivotal role in establishing and maintaining a robust communication link. Beamforming for millimeter wave communications poses a multitude of diverse challenges due to the large channel bandwidth, unique channel characteristics, and hardware constraints. In this paper, we track the evolution and advancements in antenna beamforming for millimeter wave communications in the context of the distinct requirements for indoor and outdoor communication scenarios. We expand the scope of discussion by including the developments in radio frequency system design and implementation for millimeter wave beamforming. We explore the suitability of millimeter wave beamforming methods, both, existing and proposed till midyear 2015, and identify the exciting new prospects unfolding in this domain.

Beamforming for Millimeter Wave Communications: An Inclusive Survey

This paper presents the first reported 28-GHz phased-array IC for 5G communications. Implemented in 130-nm SiGe BiCMOS, the IC includes 32 TRX elements and features concurrent independent beams in two polarizations in either TX or RX operation. Circuit techniques to enable precise beam steering, orthogonal phase and amplitude control at each front end, and independent tapering and beam steering at the array level are presented. A TX/RX switch design is introduced which minimizes TX path loss resulting in 13.5 dBm/16 dBm Op1dB/Psat per front end with >20% peak power added efficiency of the power amplifier (including switch and off-mode LNA) while maintaining a 6 dB noise figure in the low noise amplifier (including switch and off-mode PA). Comprehensive on-wafer measurement results for the IC across multiple samples and temperature variation are presented. A package with four ICs and 64 dual-polarized antennas provides eight 16-element or two 64-element concurrent beams with 1.4°/step beam steering (<0.6° rms error) across a ±50° steering range without requiring calibration. A maximum saturated effective isotropic radiated power of 54 dBm is measured in the broadside direction for each polarization. Tapering control without requiring calibration achieves up to 20-dB sidelobe rejection without affecting the main lobe direction.

A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications

A 60-GHz dual-mode power amplifier (PA) is implemented in 40-nm bulk CMOS technology. To boost the amplifier performance at millimeter-wave (mmWave) frequencies, a new transistor layout is proposed to minimize the device and interconnect parasitics while the neutralized amplifier stage is co-optimized with input transformer to improve the power gain and stability. The transformer-based power-combining PA consists of two unit amplifiers, operating in Class AB for better back-off efficiency. To further reduce the power consumption and hence extend battery lifetime, one unit PA is tuned off in low-power mode. A switch is used to short the output of this non-operating unit PA to reduce the combiner loss and improve the efficiency. The PA achieves a measured saturated output power (PSAT) of 17.0 dBm (12.1 dBm) and 1-dB compressed power (P1dB) of 13.8 dBm (9.1 dBm) in the high-power (low-power) mode. The power-added efficiencies (PAEs) at PSAT and P1dB are 30.3% and 21.6% respectively for the high-power mode. Compared to Class A, the PA operating in Class AB shows 5.3% improvement in measured PAE at P1dB with no compromise in linearity. The PA with the power combiner only occupies an active area of 0.074 mm 2. The reliability measurements are also conducted and the PA has an estimated lifetime of 80613 hours.

A 60-GHz Dual-Mode Class AB Power Amplifier in 40-nm CMOS

The IEEE 802.11ad standard supports PHY rates up to 6.7Gb/s on four 2GHz-wide channels from 57 to 64GHz. A 60GHz system offers higher throughput than existing 802.11ac solutions but has several challenges for high-volume production including: integration in the host platform, automated test, and high link loss due to blockage and polarization mismatch. This paper presents a full-featured 802.11ad chipset capable of SC and OFDM modulation using a 16TX-16RX beamforming RF front-end, complete with an antenna array that supports polarization diversity. To aid low-cost integration in PC platforms, a single coaxial cable interface is used between chips. The chipset includes MAC, PHY, and RF with a PCIeTM interface and is capable of maintaining a link of 4.6Gb/s (PHY rate) at 10m.

20.2 A 16TX/16RX 60GHz 802.11ad chipset with single coaxial interface and polarization diversity

A 60GHz short-range wireless system offers new opportunities for achieving wireless high-definition video links and multi-Gb/s wireless data transfer. Recent works have realized a 60GHz transceiver by means of a cost-effective CMOS process [1-3], but using a 60GHz system in mobile terminals poses the difficult challenge of achieving low power consumption as well as small form factor. The publication [3] achieves a power consumption of less than 756mW, but uses a simple MAC protocol incompatible with global standards and also suffers from a limited distance of less than 4cm. This paper presents a fully integrated transceiver chipset based on WiGig/IEEE802.11ad standards targeting mobile usage. The chipset is developed for a single-carrier (SC) modulation, which is suitable for reduced power consumption as compared to using OFDM modulation. However, the SC modulation is sensitive to in-band amplitude variation, mainly made worse by the gain variation of analog circuits and multipath delay spread. In order to compensate for those gain variations, the proposed chipset employs built-in TX in-band calibration and an RX frequency domain equalizer (FDE). The proposed techniques can relax the requirement for high speed analog circuits, leading to less power consumption while minimizing the increase of hardware size.

A fully integrated 60GHz CMOS transceiver chipset based on WiGig/IEEE802.11ad with built-in self calibration for mobile applications

The link budget of multi-Gb/s wireless communication systems around 60GHz improves by beamforming. CMOS realizations for this type of communication are mostly limited to either one-antenna systems [1], or beamforming ICs that do not implement all radio functions [2]. The sliding-IF architecture of [3] uses RF phase shifting, which deteriorates noise performance.

A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication

Obtaining sufficient EVM in all four 1.76GHz bandwidth channels specified by IEEE 802.15.3c and the emerging 802.11ad high-data-rate wireless communication standards for modulations as complex as QAM16 is a challenge. Recently reported implementations are therefore restricted to just 1 or 2 channels [1]. Wireless applications often use digital low-power (LP) CMOS technology to implement single-chip transceivers. The high V t and the thin metal interconnect layers constrain the mm-Wave circuit performance. This paper presents a digital LP 40nm CMOS 60GHz transceiver (TRX) IC that obtains an EVM better than −17dB in all 4 channels.

A low-power 57-to-66GHz transceiver in 40nm LP CMOS with −17dB EVM at 7Gb/s

A polar transmitter (TX) is implemented at 60 GHz, enabling a power amplifier (PA) to operate in saturation where efficiency is highest, even when handling higher order modulations such as QPSK and 16-QAM. The phase path is upconverted by I-Q mixers, while the amplitude path modulates an RF-DAC. Aimed at 802.11ad applications, the 10 GS/s (i.e., 6x-oversampled) polar TX realizes more than 30 dB alias attenuation, and the input bandwidth exceeds 3.1 GHz. The PA saturated output power is 10.8 dBm with 29.8% drain efficiency at the maximum RF-DAC code. Average output power is 8.1 dBm with 22.3% drain efficiency at $-20.7\;\text{dB}$ EVM for QPSK modulation without RF-DAC predistortion. The corresponding 16-QAM values are: 7.2 dBm average output power with 19.8% efficiency at $-16.5\;\text{dB}$ EVM. With predistortion, a QPSK modulated output achieves 5.3 dBm average power with 15.3% efficiency at $-23.6\;\text{dB}$ EVM, while 3.6 dBm average power with 11.6% efficiency at $-18.1\;\text{dB}$ EVM is realized for 16-QAM. For a sampling rate of 10 GS/s, the TX data rates are 3.33 Gb/and 6.67 Gb/s for QPSK and 16-QAM, respectively. Implemented in 40 nm bulk-CMOS, the core circuit occupies $0.18\text{mm}^{2}$ core of the $2.38\text{mm}^{2}$ total die area, and consumes 40.2 mW from a 0.9 V supply.

Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication

A 60 GHz sub-sampling PLL implemented in 40 nm CMOS is presented in this paper. The sub-sampling phase detector (SSPD) runs at 30 GHz after an inductively-peaked static divide-by-two. Thanks to the lower frequency of operation, the effect of non-zero sampling aperture of the switch is minimized. A dummy divider of the quadrature PLL is utilized for the sub-sampling loop to avoid extra loading in the 60 GHz path. A 53.8–63.3 GHz QVCO uses super-harmonic coupling at 120 GHz for relaxed headroom at a 0.9 V supply and achieves a free-running phase noise down to ${-}$ 94.5 dBc/Hz at 1 MHz offset. The millimeter-wave sub-sampling PLL achieves an RMS jitter, integrated from 1 kHz to 100 MHz, of 200 fs at a power consumption of 42 mW, compared to 210 fs for the PFD/CP PLL at 75 mW. Reference spurs in both modes are below ${-}$ 40 dBc.

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS

For high data-rate communication at 60GHz using the IEEE 802.11ad standard, the LO synthesis needs both a low-noise VCO and low in-band phase noise. In the PLL shown in this paper, a QVCO with superharmonic passive coupling exhibits a large swing and low phase noise even with a 0.9V supply. In-band phase noise is reduced thanks to the use of a sub-sampling phase detector (SSPD), earlier introduced for low-GHz PLLs [1]. As most of the divider chain and the charge pump (CP) can be powered down in the sub-sampling mode, power consumption is also reduced.

Viki Szortyka

Papers

A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication

A low-power 57-to-66GHz transceiver in 40nm LP CMOS with −17dB EVM at 7Gb/s

Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS

21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS