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Wen-Kuan Yeh
Researcher at National University of Kaohsiung
Publications - 198
Citations - 1856
Wen-Kuan Yeh is an academic researcher from National University of Kaohsiung. The author has contributed to research in topics: Silicon on insulator & MOSFET. The author has an hindex of 19, co-authored 193 publications receiving 1489 citations. Previous affiliations of Wen-Kuan Yeh include Hodges University.
Papers
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Proceedings ArticleDOI
Sub-60mV-swing negative-capacitance FinFET without hysteresis
Kai-Shin Li,Pin-Guang Chen,Tung-Yan Lai,Chang-Hsien Lin,Cheng-Chih Cheng,Chun-Chi Chen,Yun-Jie Wei,Yun-Fang Hou,Ming-Han Liao,Min-Hung Lee,Min-Cheng Chen,Jia-Min Sheih,Wen-Kuan Yeh,Fu-Liang Yang,Sayeef Salahuddin,Chenming Hu +15 more
TL;DR: In this article, negative-Capacitance FinFETs with a floating internal gate are reported, where ALD Hf042ZrO2 ferroelectricity is added on top of the gate stack.
Proceedings ArticleDOI
Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition
Haitong Li,Tony F. Wu,Abbas Rahimi,Kai-Shin Li,Miles Rusch,Chang-Hsien Lin,Juo-Luen Hsu,Mohamed M. Sabry,S. Burc Eryilmaz,Joon Sohn,Wen-Cheng Chiu,Min-Cheng Chen,Tsung-Ta Wu,Jia-Min Shieh,Wen-Kuan Yeh,Jan M. Rabaey,Subhasish Mitra,H.-S. Philip Wong +17 more
TL;DR: Hard-error analysis shows the HD architecture is amazingly resilient to RRAM endurance failures, making the use of various types of RRAMs/CBRAMs feasible, and Multiplication-addition-permutation (MAP), the central operations of HD computing, are experimentally demonstrated.
Proceedings ArticleDOI
Four-layer 3D vertical RRAM integrated with FinFET as a versatile computing unit for brain-inspired cognitive information processing
Haitong Li,Kai-Shin Li,Chang-Hsien Lin,Juo-Luen Hsu,Wen-Cheng Chiu,Min-Cheng Chen,Tsung-Ta Wu,Joon Sohn,S. Burc Eryilmaz,Jia-Min Shieh,Wen-Kuan Yeh,H.-S. Philip Wong +11 more
TL;DR: For the first time, a four-layer HfOx-based 3D vertical RRAM, the “tallest” one ever reported, is developed and integrated with FinFET selector, and Uniform memory performance across four layers is obtained.
Journal ArticleDOI
Substrate noise-coupling characterization and efficient suppression in CMOS technology
TL;DR: In this paper, the authors investigated the substrate noise coupling using S-parameters measurement and found that the noise coupling can be efficiently diminished by incorporating GR and DNW structures in the layout geometry.
Journal ArticleDOI
Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon
Che Yu Lin,Xiaodan Zhu,Shin Hung Tsai,Shiao Po Tsai,Sidong Lei,Yumeng Shi,Lain-Jong Li,Shyh-Jer Huang,Wen Fa Wu,Wen-Kuan Yeh,Yan-Kuin Su,Yan-Kuin Su,Kang L. Wang,Yann Wen Lan +13 more
TL;DR: The experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe2-MoS2 junctions as the conducting p-n channel is demonstrated, and the negative differential resistance in the electrical characteristics is observed.