An analytical modeling of charge plasma based Tunnel Field Effect Transistor with impacts of gate underlap region

Based on an analytical surface potential model incorporating the channel inversion carriers, a physics-based terminal capacitance model with closed-form solutions for a hetero-gate-dielectric (HGD) tunnel field-effect transistor (TFET) is developed for the first time. Good agreements between the proposed model and the numerical simulations have been achieved in all operation regimes and for different HGD structures. The developed model without involving any iterative process can be easily applied to the widely used SPICE simulations and would be helpful for the transient performance of TFET-based circuits.

Fully Analytical Carrier-Based Charge and Capacitance Model for Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

In this paper, a universal analytical current model for a double-gate Si-based tunnel field-effect transistor (TFET) is presented considering the effects of charges in source depletion region and channel. An accurate surface potential model is developed first by solving the pseudo-2-D Poisson equations in the depletion regions, and then is used to calculate the drain tunneling current. The modeling results match well with that obtained from the Technology computer-aided design simulations under various biasing conditions, which indicate that the analytical current model would be very helpful for the further TFET-based circuits design. Furthermore, the influence of the source depletion is also studied, and the presented model with considering the source depletion region and the channel inversion charges is proved to be much more accurate than that ignoring the source depletion.

A Fully Analytical Current Model for Tunnel Field-Effect Transistors Considering the Effects of Source Depletion and Channel Charges

A novel analytical approach to optimize the work functions of dual-material double-gate Tunneling-FETs

The practical use of tunnel field-effect transistors is retarded by the low on-state current. In this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure of source-pocket concept are combined in a single tunnel field-effect transistor to extensively boost the device performance. The proposed device shows improved tunnel on-state current and subthreshold swing. In addition, analytical potential model for the proposed device is developed and tunneling current is also calculated. Good agreement of the modeled results with numerical simulations verifies the validation of our model. With significantly reduced simulation time while acceptable accuracy, the model would be helpful for the further investigation of TFET-based circuit simulations.

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Based on an analytical surface potential and a simple mathematical approximation for the source depletion width, a physics-based capacitance model with closed form for silicon double-gate tunnel field-effect transistors (TFETs) is developed. Good agreements between the proposed model and the numerical simulations have been achieved, which reveal that the tunneling carriers from source have negligible contribution to the channel charges and the gate capacitance can be almost acted as the gate–drain capacitance, which is quite different from that of MOSFETs. This model without involving any iterative process is more SPICE friendly for circuit simulations compared with the table-lookup approach and would be helpful for developing the transient performance of TFET-based circuits.

A Charge-Based Capacitance Model for Double-Gate Tunnel FETs With Closed-Form Solution

Improved analytical model of surface potential with modified boundary conditions for double gate tunnel FETs

The invention discloses a metal oxide semiconductor field effect transistor. The metal oxide semiconductor field effect transistor comprises a substrate (9) and a channel layer (7) from the bottom up, wherein a source region (5) and a drain region (6) are arranged at the two ends of the channel layer (7); a source electrode (1) and a drain electrode (3) are arranged right above the source region and the drain region respectively; a gate oxide layer (4) is arranged between the source electrode and the drain electrode; a gate electrode (2) is arranged right above the gate oxide layer, wherein a buffer layer (8) is additionally arranged between the substrate and the channel layer; the buffer layer (8) adopts a GaAs material; the channel layer (7) adopts an In Ga As material; the doping material is boron or phosphorus; the doping concentration is 10 -10 cm ; and the gate oxide layer (4) adopts a high-K material with a dielectric constant which is greater than 3.9. According to the metal oxide semiconductor field effect transistor, the interface trapping charge between the channel layer and the high-K gate oxide layer is reduced; the electrical performance degradation phenomenon of the metal oxide semiconductor field effect transistor is reduced; and the metal oxide semiconductor field effect transistor can be applied to the manufacturing of large-scale integrated circuits.

Xiaoran Cui

Papers

A Charge-Based Capacitance Model for Double-Gate Tunnel FETs With Closed-Form Solution

Fully Analytical Carrier-Based Charge and Capacitance Model for Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

A Fully Analytical Current Model for Tunnel Field-Effect Transistors Considering the Effects of Source Depletion and Channel Charges

Improved analytical model of surface potential with modified boundary conditions for double gate tunnel FETs

Metal oxide semiconductor field effect transistor and manufacturing method therefor