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Design Of Analog Cmos Integrated Circuits

The rapid development of information technology has led to urgent requirements for high efficiency and ultralow power consumption. In the past few decades, neuromorphic computing has drawn extensive attention due to its promising capability in processing massive data with extremely low power consumption. Here, we offer a comprehensive review on emerging artificial neuromorphic devices and their applications. In light of the inner physical processes, we classify the devices into nine major categories and discuss their respective strengths and weaknesses. We will show that anion/cation migration-based memristive devices, phase change, and spintronic synapses have been quite mature and possess excellent stability as a memory device, yet they still suffer from challenges in weight updating linearity and symmetry. Meanwhile, the recently developed electrolyte-gated synaptic transistors have demonstrated outstanding energy efficiency, linearity, and symmetry, but their stability and scalability still need to be optimized. Other emerging synaptic structures, such as ferroelectric, metal–insulator transition based, photonic, and purely electronic devices also have limitations in some aspects, therefore leading to the need for further developing high-performance synaptic devices. Additional efforts are also demanded to enhance the functionality of artificial neurons while maintaining a relatively low cost in area and power, and it will be of significance to explore the intrinsic neuronal stochasticity in computing and optimize their driving capability, etc. Finally, by looking into the correlations between the operation mechanisms, material systems, device structures, and performance, we provide clues to future material selections, device designs, and integrations for artificial synapses and neurons.

A comprehensive review on emerging artificial neuromorphic devices

https://research.aalto.fi/files/19264492/The_rich_photonic_world_of_plasmonic.pdf

The rich photonic world of plasmonic nanoparticle arrays

Near-field photocurrent nanoscopy is used for imaging strongly confined terahertz graphene plasmons with linear dispersion.

/pdf/acoustic-terahertz-graphene-plasmons-revealed-by-4fp3i9bvzl.pdf

Acoustic terahertz graphene plasmons revealed by photocurrent nanoscopy

The field of visible light communications (VLC) has gained significant interest over the last decade, in both fibre and free-space embodiments. In fibre systems, the availability of low cost plastic optical fibre (POF) that is compatible with visible data communications has been a key enabler. In free-space applications, the availability of hundreds of THz of the unregulated spectrum makes VLC attractive for wireless communications. This paper provides an overview of the recent developments in VLC systems based on gallium nitride (GaN) light-emitting diodes (LEDs), covering aspects from sources to systems. The state-of-the-art technology enabling bandwidth of GaN LEDs in the range of >400 MHz is explored. Furthermore, advances in key technologies, including advanced modulation, equalisation, and multiplexing that have enabled free-space VLC data rates beyond 10 Gb/s are also outlined.

/pdf/a-review-of-gallium-nitride-leds-for-multi-gigabit-per-4fgs6zvkvk.pdf

A review of gallium nitride LEDs for multi-gigabit-per-second visible light data communications

Light-emitting diodes [LEDs] are of particular interest recently as their performance is approaching fluorescent/incandescent tubes. Moreover, their energy-saving property is attracting many researchers because of the huge energy crisis we are facing. Among all methods intending to enhance the efficiency and intensity of a conventional LED, localized surface plasmon resonance is a promising way. The mechanism is based on the energy coupling effect between the emitted photons from the semiconductor and metallic nanoparticles fabricated by nanotechnology. In this review, we describe the mechanism of this coupling effect and summarize the common fabrication techniques. The prospect, including the potential to replace fluorescent/incandescent lighting devices as well as applications to flat panel displays and optoelectronics, and future challenges with regard to the design of metallic nanostructures and fabrication techniques are discussed.

/pdf/light-emitting-diodes-enhanced-by-localized-surface-plasmon-4adn6g03wo.pdf

Light-emitting diodes enhanced by localized surface plasmon resonance

A deep subwavelength terahertz plasmonic waveguide based on graphene-metal hybrid structure is proposed. A broadband mode confinement down to 1/100 of the free-space wavelength λ0 with a loss of 0.6 dB/λ0 can be achieved when the intra-band electron relaxation time is 100 ps. We show that very narrow slits with an appropriate periodicity created in the metal layer can serve as a grating to efficiently excite the surface plasmon-polariton mode with a normally incident terahertz beam, which can be further exploited for investigation of both interesting physics and innovative applications.

Extremely confined terahertz surface plasmon-polaritons in graphene-metal structures

Unsupervised learning is demonstrated using a device ubiquitously found in today’s technology: a transistor with high- ${k}$ -metal gate. Specifically, the charge-trapping phenomenon in the high- ${k}$ gate dielectric is leveraged so that the device can be used as a non-volatile analog memory. Experimental data from 22-nm silicon-on-insulator devices reveal that a charge-trap transistor possesses promising characteristics for implementing synapses in neural networks, such as very fine tunability, weight-dependent plasticity, and low power consumption. A proof-of-concept winner-takes-all neural network is simulated based on experimental data and perfect clustering is achieved within tens of training cycles. This means that the network can be trained for multiple times, and a larger system can be built. The robustness of the procedure to the device variation is also discussed.

/pdf/unsupervised-learning-using-charge-trap-transistors-pkxdtg52rj.pdf

Unsupervised Learning Using Charge-Trap Transistors

An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog–digital interfaces. By implementing the sequential analog fabric, the engine’s mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 784 by 784 CTT computing engine is implemented using TSMC 28-nm CMOS technology and occupies 0.68 mm2. The simulated performance achieves 76.8 TOPS (8-bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem—classifying handwritten digits on MNIST database and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.

An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)

Since our demonstration of unsupervised learning using the CMOS-only charge-trap transistors (CTTs) as analog synapses, there has been an increasing interest in exploiting the device for various other neural network (NN) applications. However, most of these studies are limited to mere simulation due to the absence of detailed experimental device characterization. In this article, we provide a comprehensive investigation of the programming behavior of CTTs, including analog retention, intra- and inter-device variation, and fine-tuning of the device, both for individual devices and for devices in an integrated array. It is found that, after programming, the channel current gradually increases to a higher level, and the shift is larger when the device is programmed to a higher threshold voltage. With this postprogramming current increase appropriately accounted for, individual devices can be programmed to an equivalent precision of five bits, and three bits can be achieved for devices in an array. Our results reveal the promising future of using the CTT as a CMOS-only analog memory device.

Xuefeng Gu

Papers

Light-emitting diodes enhanced by localized surface plasmon resonance

Extremely confined terahertz surface plasmon-polaritons in graphene-metal structures

Unsupervised Learning Using Charge-Trap Transistors

An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)

Charge-Trap Transistors for CMOS-Only Analog Memory