Showing papers by "Yihwan Kim published in 2013"
TL;DR: The semiconductor processing technology presented in this work provides a robust method for fabrication of innovative Ge(1-x)Sn(x) nanostructures whose realization can prove to be challenging, if not impossible, otherwise.
Abstract: We present a new etch chemistry that enables highly selective dry etching of germanium over its alloy with tin (Ge1–xSnx). We address the challenges in synthesis of high-quality, defect-free Ge1–xSnx thin films by using Ge virtual substrates as a template for Ge1–xSnx epitaxy. The etch process is applied to selectively remove the stress-inducing Ge virtual substrate and achieve strain-free, direct band gap Ge0.92Sn0.08. The semiconductor processing technology presented in this work provides a robust method for fabrication of innovative Ge1–xSnx nanostructures whose realization can prove to be challenging, if not impossible, otherwise.
92 citations
TL;DR: In this article, the authors report on the characterization of high Sn-content (∼10% Sn) GeSn films grown on (001) Ge/Si substrates using reduced-pressure chemical vapor deposition.
79 citations
TL;DR: Germanium tin (GeSn) pMOSFETs with channel Sn composition of 7% were fabricated using a low thermal budget process in this paper, which showed an improvement in hole mobility over control Ge devices by 85% in high inversion charge density regime.
Abstract: Germanium tin (GeSn) pMOSFETs with channel Sn composition of 7% are fabricated using a low thermal budget process. GeSn pMOSFETs show enhancement in hole mobility over control Ge devices by 85% in high inversion charge density regime. Hole mobility improvement observed in GeSn channel pMOSFETs compared with Ge control is due to the biaxial compressive strain in GeSn resulting from epitaxial growth of GeSn thin films on relaxed Ge buffer layers.
67 citations
TL;DR: In this paper, a Si n-i-p tunnel field effect transistor (TFET) fabricated by plasma implantation and laser annealing is proposed, which has sharp lateral source doping profile, which can reduce the tunneling distance and improve carrier tunneling.
Abstract: Si n–i–p tunnel field-effect transistor (TFET) fabricated by plasma implantation and laser annealing is proposed. This TFET has sharp lateral source doping profile, which can reduce the tunneling distance and improve carrier tunneling. Enhanced on-current (12 μA/μm) and improved I ON / I OFF ratio (6 × 10 6 ) are observed in this TFET [ V DS = ( V GS − V BTBT ) = −1.1 V; V BTBT is the V GS at the lowest subthreshold current observed at given V DS ] at T = 300 K. In addition, the TFET fabricated by laser annealing shows improved subthreshold characteristics, reduced tunneling resistance and smaller threshold voltage than TFET fabricated by rapid thermal annealing. Low-temperature measurements of this TFET were also performed to confirm the carrier injection mechanism of band-to-band tunneling. Plasma implantation and laser annealing are effective and suitable to be applied in current CMOS technology for low power devices.
13 citations
Proceedings Article•
11 Jun 2013TL;DR: In this paper, the authors demonstrate the low temperature fabrication of high quality GeSn-On-Insulator (GSOI) which forms the crucial module for monolithic 3DIC.
Abstract: In this work, we demonstrate the low temperature fabrication of high quality GeSn-On-Insulator (GSOI) which forms the crucial module for monolithic 3DIC. The use of GeSn and Ge overcomes many challenges of monolithic 3D integration, including the need for Si-compatible high-mobility and direct gap materials. Furthermore, we introduce excellent passivation of the semiconductor/buried oxide (BOX) interface which is crucial to the high performance of devices on the stacked layers.
9 citations
TL;DR: The segmented-channel MOSFETs show better layout efficiency, enhanced hole mobility and dramatically reduced dependence of performance on layout width due to the geometrical regularity of the channel region.
Abstract: Segmented-channel Si1-xGex/Si p-channel MOSFETs are fabricated using a conventional process, starting with corrugated Si1-xGex/Sisubstrates. As compared with the control devices fabricated using the same process but starting with a noncorrugated Si1-xGex/Si substrate, the segmented-channel MOSFETs show better layout efficiency (30% higher ION for IOFF = 10 nA per micrometer layout width) due to enhanced hole mobility and dramatically reduced dependence of performance on layout width due to the geometrical regularity of the channel region.
6 citations
Proceedings Article•
11 Jun 2013TL;DR: In this article, SegFETs are compared against control devices fabricated using the same process but starting with non-corrugated substrates, with respect to key analog/RF performance metrics.
Abstract: Segmented-channel Si and SiGe P-MOSFETs (SegFETs) are compared against control devices fabricated using the same process but starting with non-corrugated substrates, with respect to key analog/RF performance metrics. SegFETs are found to have significant benefits due to their enhanced electrostatic integrity, lower series resistance and greater mobility enhancement, and hence show promise for future System-on-Chip applications.
2 citations