International Conference on Solid-State and Integrated Circuits Technology 

About: International Conference on Solid-State and Integrated Circuits Technology is an academic conference. The conference publishes majorly in the area(s): CMOS & MOSFET. Over the lifetime, 2612 publications have been published by the conference receiving 7404 citations.

Proximity effect in electron beam lithography

Abstract: Proximity effect is the most severe factor that influences the exposure resolution of electron beam. In this paper, the mechanism of proximity effect is discussed through Monte Carlo simulation of the electron scattering processes. And effective approaches of proximity effect correction are proposed. The theoretical results of Monte Carlo simulation and experimental results show that proximity effect is determined by many factors, in addition to the shape, size and packing density of patterns, proximity effect is also dependent on processes conditions. Only on the basis of optimizing the processes conditions and mask design, the expectant purpose of proximity effect correction by software can be achieved. Proximity effect is effectively reduced through improving mask design, optimizing processes conditions and utilizing proximity effect correction software.

Novel InSb-based quantum well transistors for ultra-high speed, low power logic applications

Abstract: InSb-based quantum well field-effect transistors, with gate length down to 0.2 /spl mu/m, are fabricated for the first time. Hall measurements show that room temperature electron mobilities over 30,000 cm /sup 2/V/sup -1/s/sup -1/ are achieved with a sheet carrier density over 1/spl times/10/sup 12/ cm/sup -2/ in a modulation doped InSb quantum well with Al/sub x/In/sub 1-x/Sb barrier layers. Devices with 0.2 /spl mu/m gate length and 20% Al barrier exhibit DC transconductance of 625 /spl mu/S//spl mu/m and f/sub T/ of 150 GHz at V/sub DS/ =0.5V. 0.2 /spl mu/m devices fabricated on 30% Al barrier material show DC transconductance of 920 /spl mu/S//spl mu/m at V/sub DS/ = 0.5 V. Benchmarking against state-of-the-art Si MOSFETs indicates that InSb QW transistors can achieve equivalent high speed performance with 5-10 times lower dynamic power dissipation and therefore are a promising device technology to complement scaled silicon-based devices for very low power, ultra-high speed logic applications.

Overcoming research challenges for CMOS scaling: industry directions

Abstract: The development of silicon technology has been, and will continue to be, driven by system needs. The continuous and systematic increase in transistor density and performance, guided by CMOS scaling theory (Dennard et al., 1974) and described in "Moore's Law" (Moore, 1975), has been a highly successful process for the development of silicon technology for the past 40 years. As the silicon industry moves into the 45 nm node and beyond, significant technology challenges are imposed by silicon CMOS device scaling. Two of the most important challenges are the growing standby power dissipation and the increasing variability in device characteristics. These complaints are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. They are frequently cited as the reason Moore's Law is "broken", or why CMOS scaling is coming to an end. Industry directions for addressing these challenges are developing along three primary extending silicon scaling through innovations in materials and device structure; expanding the level of integration through three-dimensional structures comprised of silicon through-via holes and chip stacking in order to enhance functionality and parallelism; and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials, and new processes, such as spintronics, carbon nanotubes, nanowires, or molecular systems

Highly Efficient and Linear Class E SiGe Power Amplifier Design

Abstract: This paper discusses the design of monolithic RF broadband Class E SiGe power amplifiers (PAs) that are highly efficient and linear. Load-pull measurement data on IBM 7HP SiGe power devices have been made at 900MHz and 2.4GHz and monolithic class E PAs have been designed using these devices to achieve highest power-added-efficiency (PAE) at these frequencies. It is found that high PAE can be achieved for monolithic single-stage Class E PAs designed using high-breakdown SiGe transistors at ~65% (900MHz) and ~40% (2.4GHz), respectively, which are roughly ~10% lower than the device's maximum PAE values obtained by load-pull tests under optimal off-chip matching conditions. We have also demonstrated that monolithic SiGe class E PAs can be successfully linearized using an open-loop envelope tracking (ET) technique as their output spectra pass the stringent EDGE transmit mask with margins, achieving overall PAE of 44.4% for the linearized PA system that surpasses the < 30% PAE with commercially available GaAs Class AB PAs for EDGE applications. These promising results indicate the feasibility of realizing true single-chip wireless transceivers with on-chip RF SiGe PAs for spectrally-efficient non-constant-envelope modulation schemes

CMOS-compatible zero-mask One Time Programmable (OTP) memory design

Abstract: A method to design CMOS-compatible diode-based One-Time Programmable (OTP) memory is discussed in this paper. In particular the program disturb problem is resolved by using diode drivers with sufficiently high breakdown voltage. The choices of memory elements and various available diodes in a standard CMOS process are carefully studied to obtain an optimal combination. Different memory cells were fabricated in standard 0.18-?m CMOS technology to verify the functionality of the design.