Showing papers in "Iet Circuits Devices & Systems in 2015"

Thermal properties of graphene and few-layer graphene: applications in electronics

Abstract: The authors review thermal properties of graphene and few-layer graphene (FLG), and discuss applications of these materials in thermal management of advanced electronics. The intrinsic thermal conductivity of graphene - among the highest of known materials - is dominated by phonons near the room temperature. The examples of thermal management applications include the FLG heat spreaders integrated near the heat generating areas of the high-power density transistors. It has been demonstrated that FLG heat spreaders can lower the hot-spot temperature during device operation, resulting in improved performance and reliability of the devices.

Graphene electronic sensors – review of recent developments and future challenges

Abstract: Electronic sensors based on graphene have a high potential in many applications, due to the unique properties of the graphene material. This study is a review where the authors discuss the properties of graphene which are useful to sensing applications and they report and describe different types of graphene electronic sensors: biological, mechanical, gas and chemical sensors. They also discuss the ways to functionalise graphene and the used device structures. They compare the performance of the main types of biological, mechanical and chemical sensors. Finally, they explain the future challenges of graphene-based sensors, in order to make graphene sensing systems and smart sensors, which would be their main breakthrough application.

Energy storage and loss in fractional-order circuit elements

Abstract: The efficiency of a general fractional-order circuit element as an energy storage device is analysed. Simple expressions are derived for the proportions of energy that may be transferred into and then recovered from a fractional-order element by either constant-current or constant-voltage charging and discharging. For a half-order element, it is shown that the efficiency of the charging phase of the cycle is equal to the efficiency of the discharging phase. The results demonstrate the duality of the fractional capacitive and inductive elements, in that the efficiency of one under constant-current cycling is the same as the efficiency of the other under constant-voltage cycling, and vice-versa.

Approach for third order quadrature oscillator realisation

Abstract: This paper presents a new approach for third order quadrature oscillator (QO) realisation. It uses a high pass filter and differentiator connected in a feedback loop. A differential voltage current conveyor transconductance amplifier (DVCCTA) is employed to verify the proposed approach. Two circuit topologies of QO have been proposed. Both the topologies utilise two DVCCTA and three grounded capacitors. In addition, the first topology employs a single resistor while the second makes use of two resistors. The circuits exhibit orthogonal control on frequency and condition of oscillation. The quadrature current outputs are available at high output impedance and voltage outputs are also present. The theoretical proposition has been verified through SPICE simulations using 0.25 μm Taiwan semiconductor manufacturing company (TSMC) complementary metal oxide semiconductor (CMOS) technology parameters. Experimental results are also included which corroborate the theoretical propositions and simulated results.

Is graphene a good transparent electrode for photovoltaics and display applications

Abstract: The current standard material used for transparent electrodes in displays, touch screens and solar cells is indium tin oxide (ITO) which has low sheet resistance (10 Ω/□), high optical transmission in the visible wavelength (85%) and does not suffer of optical haze. However, ITO is mechanically rigid and incompatible with future demands for flexible applications. Graphene materials share many of the properties desirable for flexible transparent conductors, including high optical transparency, high mechanical flexibility and strength. Whilst pristine graphene is not a good transparent conductor, functionalised graphene is at least 1000 times a better conductor than its pristine counterpart and it outperforms ITO. Here the authors review recent work on a novel graphene-based conductor with sheet resistance as low as 8.8 Ω/□ and 84% optical transmission. This material is obtained by ferric chloride (FeCl3) intercalation into few-layer-graphene (FLG), giving rise to a new system which is the best known flexible and transparent electricity conductor. FeCl3-FLG shows no significant changes in the electrical and structural properties for a long exposure to air, to high levels of humidity and at temperatures of up to 150°C in atmosphere. These properties position FeCl3-FLG as a viable and attractive replacement to ITO.

Graphene-based biosensors: Methods, analysis and future perspectives

Abstract: Graphene (GN), a single layer two-dimensional structure nanomaterial, exhibits exceptional physical, electrical and chemical properties that lead to many applications from electronics to biomedicine. The unique parameters of GN, notably its considerable electron mobility, thermal conductivity, high surface area and electrical conductivity, are bringing heightened attention into biomedical applications. This study assesses the recent advances in GN-based biosensors and its derivatives in different areas to focus on glucose sensing, DNA sensing, drug and gene delivery, cancer therapy and other related biomedical applications (electrochemical sensors, tissue engineering, haemoglobin and cholesterol sensing), together with a brief discussion on challenges and future perspectives in this rapidly developing field.

Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells

Abstract: Modern digital circuits are facing aggressive technology and voltage scaling under emerging technology generations. This study proposes a circuit-level technique to mitigate the adverse effects of process, voltage and temperature (PVT) variations on the design metrics of full adder (FA) cells under such ultra-deep sub-micron technology nodes. The proposed FA cells exhibit improved variability because of the use of inverting low voltage Schmitt trigger sub-circuits incorporated in the designs in place of inverters. The proposed circuits have been designed to operate in the near-threshold region, which offers a trade-off between performance and power consumption. The comparative analysis based on Monte Carlo simulations in a SPICE environment, using the 16-nm complementary metal-oxide semiconductor predictive technology model, demonstrates that the proposed technique is capable of mitigating the impact of PVT variations on major design metrics such as power, delay and power-delay product in FA cells. This improvement is achieved at the expense of two extra transistors for every replaced inverter in the FA cell.

Three-state quantum dot gate field-effect transistor in silicon-on-insulator

Abstract: This paper presents the observation of intermediate state in the quantum dot gate field-effect transistors (QDGFETs) in silicon-on-insulator (SOI) substrate. Silicon dioxide (SiO2)-cladded silicon (Si) quantum dots (QDs) are site-specifically self-assembled on the top of SiO2 tunnel gate insulator on SOI substrates. Charge carrier tunnelling from the inversion channel to the QD layers on top of the gate insulator is responsible for the generation of intermediate state. Charge tunnelling is also verified by the C–V characteristics of the MOS device having same insulator structure as the gate region of the QDGFET. Considering the transfer of charge carriers from the inversion channel to two layers of SiO2-cladded Si QDs, a model based on self-consistent solution of Schrodinger and Poisson equations, is also presented, to explain the generation of intermediate state.

Ultralow-power fast-transient output-capacitor-less low-dropout regulator with advanced adaptive biasing circuit

Abstract: An ultra-low-power fast-transient output-capacitor-less low-dropout regulator (LDO) with advanced adaptive biasing (AAB) circuit is presented in this study. At light load, the AAB circuit only delivers 0.1 μA bias current to the amplifier to maintain the stability and reduce the quiescent current. At medium load to heavy load, the AAB circuit increases bias current to 2.5 μA for performance enhancement. A simple but effective hysteresis current comparator is proposed to eliminate the metastable region between the bias current transitions. When output voltage recovers from overshoot, the settling time at minimum load current of 1 μA is too long because of the 100-pF load capacitor. Hence, a gradually descending load current is delivered by AAB circuit for regulating output voltage from overshoot to the nominal value promptly. The proposed circuit has been implemented in a mixed-signal 0.13-μm CMOS process. From the measurement results, the proposed LDO regulates the output voltage at 0.8 V from a 1-V input with 2.9 μA quiescent current at minimum load. Output voltage could be fully recovered within 1.7 μs at a voltage spike <;120 mV where load current switches from 1 μA to 100 mA in 800 ns.

Decoder architecture for generalised concatenated codes

Abstract: This paper proposes a pipelined decoder architecture for generalised concatenated (GC) codes. These codes are constructed from inner binary Bose–Chaudhuri–Hocquenghem (BCH) and outer Reed–Solomon codes. The decoding of the component codes is based on hard decision syndrome decoding algorithms. The concatenated code consists of several small BCH codes. This enables a hardware architecture where the decoding of the component codes is pipelined. A hardware implementation of a GC decoder is presented and the cell area, cycle counts as well as the timing constraints are investigated. The results are compared to a decoder for long BCH codes with similar error correction performance. In comparison, the pipelined GC decoder achieves a higher throughput and has lower area consumption.

Uncalibrated operational amplifier-based sensor interface for capacitive/resistive sensor applications

Abstract: In this paper, a new configuration of operational amplifier -based square-wave oscillator is proposed. The circuit performs an impedance-to-period (Z–T) conversion that, instead of a voltage integration typically performed by other solutions presented in the literature, is based on a voltage differentiation. This solution is suitable as first analogue uncalibrated front-end for capacitive and resistive (e.g. relative humidity and gas) sensors, working also, in the case of capacitive devices, for wide variation ranges (up to six capacitive variation decades). Moreover, through the setting of passive components, its sensitivity can be easily regulated. Experimental measurements, conducted on a prototype printed circuit board, with sample passive components and using the commercial capacitive humidity sensor Honeywell HCH-1000, have shown good linearity and accuracy in the estimation of capacitances, having a baseline or reaching a value ranging in a wide interval [picofarads–microfarads], as well as, with a lower accuracy, in the evaluation of more reduced variations of resistances, ranging from kiloohms to megaohms, also when compared with other solutions presented in the literature.

Approximate calculation of the potential profile in a graphene-based device

Abstract: The study of the transport and noise properties of graphene-based devices requires the computation of the potential profile as a function of the applied bias voltages. However, an exact solution for the potential profile involves a complete self-consistent treatment of the electrostatic and transport equations, which is computationally very expensive. Here, generalising the approach proposed by Das et al., the authors describe an approximate method that allows the evaluation of the potential profile by properly modifying, as a function of the bias voltages applied to the gates, the profile for a reference bias point, which is supposed to be known. The proposed approach is not very demanding from the computational point of view and can be useful for simulations aimed at the interpretation of experimental results or at device design.

Design of a 56 Gbit/s 4-level pulse-amplitude-modulation inductor-less vertical-cavity surface-emitting laser driver integrated circuit in 130 nm BiCMOS technology

Abstract: This paper presents the design and analysis of a 4-level pulse-amplitude-modulation (4-PAM) 56 Gbit/s vertical-cavity surface-emitting laser (VCSEL) driver integrated circuit (IC) for short range, high speed and low power optical interconnections. An amplitude modulated signal is necessary to overcome the bottleneck of speed given by the actual VCSELs and decrease the power consumption per bit. A prototype IC is developed in a standard 130 nm BiCMOS technology. The circuit converts two single-ended input signals to a 4-level signal fed to the laser. The driver also provides the DC current and the voltage necessary to bias the VCSEL. The power dissipation of the driver is only 115 mW including both the VCSEL and the 50 Ω input single-to-differential-ended converters. To the author's knowledge this is the first 56 Gbit/s 4-PAM laser driver implemented in silicon with a power dissipation per data-rate (DR) of 2.05 mW/Gbit/s including the VCSEL making it the most power efficient, 56 Gbit/s, common cathode laser driver. The active area occupies 0.056 mm 2 . The small signal bandwidths are 49 GHz for the high and 43 GHz for the low amplitude amplification path, when the VCSEL is not connected. The bit error rate was tested electrically showing and error free connection at 28 GBaud/s.

Low-power CMOS variable gain amplifier based on a novel tunable transconductor

Abstract: A CMOS variable gain amplifier (VGA) based on a novel linear and tunable triode transconductor is presented. The proposed transconductor employs local negative feedback for linearisation controlling the drain voltage of the input transistors biased in the triode region. The new design is able to operate at low supply voltage and the stability is guaranteed. The transconductor features a 47.75 dB dc gain and a 4.23 MHz unity gain frequency with a power consumption of only 91 µA. To show the feasibility of the proposed transconductor, a VGA has been fabricated. Measurement results for a 0.13 µm CMOS design show a −3 dB bandwidth above 2.8 MHz and a third-order harmonic distortion at 500 kHz below −46 dB over the whole gain range. The VGA exhibits a maximum power consumption of only 395 µW from a single 1.2 V supply.

Charge transport mechanism of hydrazine hydrate reduced graphene oxide

Abstract: Chemically assisted graphene oxide (GO) is synthesised by improved Hummers’ method. It has been further reduced by hydrazine hydrate by hydrothermal method to form reduced GO (rGO). Raman spectra of GO and rGO suggest the formation of D-band and G-band at 1360 and 1590 cm−1, respectively. Along with D and G modes, 2D and D′ + G′ modes have been observed at 2710 and 2950 cm−1, respectively. Tuinstra and Koenig relation is used to calculate the relative size of the sp2-carbon domain. Scanning electron micrographs reveal the separation of flakes during reduction. The dc conductivity measurement covers the peculiar study of conduction mechanism of rGO. On reduction, a remarkable increase in the room temperature conductivity (from 4.25 × 10−10 to1.9 × 10−2 S/cm) of GO has been observed. The accomplish study of dc conductivity measurement of rGO in the temperature range of 77–400 K is reported. It is explained on the basis of 3D variable range hopping model. The slope of a plot between activation energy and temperature on logarithmic scale is found to be 0.75 which suits well with the theoretical result.

Doping stability and opto-electronic performance of chemical vapour deposited graphene on transparent flexible substrates

Abstract: The primary barrier to wider commercial adoption of graphene lies in reducing the sheet resistance of the transferred material without compromising its high broad-band optical transparency, ideally through the use of novel transfer techniques and doping strategies. Here, chemical vapour deposited graphene was uniformly transferred to polymer supports by thermal and ultraviolet (UV) approaches and the time-dependent evolution of the opto-electronic performance was assessed following exposure to three kinds of common dopants. Doping with FeCl3 and SnCl2 showed minor, and notably time unstable, enhancement in the σ opt/σ dc figure of merit, while AuCl3-doping markedly reduced the sheet resistance by 91.5% to 0.29 kΩ/sq for thermally transferred samples and by 34.4% to 0.62 kΩ/sq for UV-transferred samples, offering a means of realising viable transparent flexible conductors that near the indium tin oxide benchmark.

High-speed low-power very-large-scale integration architecture for dual-standard deblocking filter

Abstract: H.264/AVC is regarded as a popular video coding standard, and is widely used in multimedia applications. However, with an increasing demand for better quality videos, high efficiency video coding (HEVC) is all set to serve as the successor to H.264/AVC for higher resolution video applications. Since a majority of the multimedia devices have already been operating based on the H.264/AVC standard, it may not be worthwhile to completely replace the existing software and hardware components by different modules in order to adopt HEVC in such devices. Need is therefore felt to design a decoder for supporting H.264/AVC as well as HEVC, rather than attempting individual designs. This paper introduces a new dual-standard deblocking filter architecture, which supports both H.264/AVC and HEVC standards. Algorithmic verification has been done in Matlab and then an appropriate VLSI architecture has been implemented on FPGA as well as in ASIC domain. The proposed architecture takes 26 clock cycles for H.264/AVC and 14 cycles for HEVC to complete the filtering of a 16 × 16 pixel block. It consumes 5.80 mW normalised power and occupies an area equivalent to 70.1k equivalent gate at frequency of 100 MHz. The proposed architecture takes 8.42 ms to filter the 4K ultra high definition (UHD) (3840 × 2160) frame in H.264 standard, and it takes 18 ms to filter the 8K UHD (7680 × 4320) frame in HEVC standard.

Graphene oxide thin films for resistive memory switches

Abstract: Dr Indrani Banerjee is grateful to Commonwealth Association, UK for funding the present research work under the fellowship placement scheme (grant reference INCF-2014-66)

Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design

Abstract: The previously proposed charge-sharing symmetric adiabatic logic (CSSAL) in an 8-bit S-box circuit is implemented in this paper using a multi-stage positive polarity Reed–Muller representation with a composite field technique. The CSSAL and other conventional dual-rail adiabatic logics are evaluated from the view point of the transitional power fluctuation and the peak current traces in the 8-bit S-box in order to compare their resistance against side-channel attacks. A method to eliminate unwanted glitch current, the triple power clock supplies are applied to each inversion block; thus, the CSSAL S-box circuit performs uniform peak current traces and it has significant power reduction, which is applicable for high security demand and low power devices, such as smart cards, radio frequency identity tags or wireless sensors. The results are obtained from the SPICE simulation with a 0.18-μm 1.8-V standard complementary metal–oxide semiconductor technology at an operating frequency band of 1.25 KHz–70 MHz.

Improving logic function synthesis, through wire crossing reduction in quantum-dot cellular automata layout

Abstract: Quantum-dot cellular automata, as the successor of metal–oxide semiconductor field-effect transistors, are one of the promising nanotechnology devices, which have attracted myriad researchers in the recent decade. In this technology, coplanar wire crossing is one of the unique specifications that can reduce its reliability. In the present study, a heuristic method is introduced using the Karnaugh-Map (K-Map) to minimise the number of wire crossing as the first step. Afterwards, it attempts to replace each wire crossing with three non-wire crossing XOR gates that reduce all wire crossings to zero as the second step. Experimental results reveal that, reducing wire crossings to zero, the authors method for 3-variable functions lowers the number of gates about 54, 42, 58 and 59%, respectively, in comparison with K-Map, Genetic, Gate-Optimise and Universal Quantum-dot Cellular Automata Logic Gate (UQCALG) methods. For 4-variable functions, their method decreases the number of gates almost 64 and 58%, respectively.

Self-supporting graphene films and their applications

Abstract: Graphene, a self-supporting monolayer, has excited enormous interest over the ten years since its discovery due to its remarkable electrical, mechanical thermal and chemical properties. Here we describe our work developing chemical vapour deposition (CVD) methods to grow monolayer graphene on copper foil substrates and the subsequent transfer process. Raman microscopy, scanning electron microscopy (SEM) and atomic force microscopy (AFM) are used to examine the quality of the transferred material. To demonstrate the process we also describe transfer onto patterned SiO2/Si substrate which forms free suspended graphene drums. These show interesting mechanical properties which are being explored as nanomechanical resonators.

Enhanced challenge-response set and secure usage scenarios for ordering-based ring oscillator-physical unclonable functions

Abstract: The number of applicable challenge–response pairs (CRPs) in physical unclonable functions (PUFs) is critical especially for authentication protocols in security systems. Ideally, full read-out of all CRPs should be infeasible and CRPs should be independent from each other for a highly secure system. CRP concept is not defined in ordering-based ring oscillator (RO) PUFs presented in the literature. In this paper, the authors propose two methods for enhanced CRP set in ordering-based RO-PUFs and analyse their performance in terms of uniqueness and area efficiency. Next, they propose three secure usage scenarios based on enhanced CRP set methods, preventing the CRPs from leaking information about each other. With the proposed systems, 100% robust, area and power efficient and secure PUF structures with exponential number of CRPs become possible that are very convenient especially for authentication protocols.

Graphene oxide-based non-volatile organic field effect memory transistors

Abstract: To produce organic non-volatile organic memory transistors, graphene oxide (GO) nanoparticles were embedded in the floating gate of an all organic memory structure using polymethylmethacrylate as the dielectric and pentacene as the organic semiconductor. The current–voltage characteristics and the memory behaviour of the GO-based organic thin film memory transistors are reported. GO-based memory transistors were shown to produce reliable and large memory windows by virtue of high capacity and reduced charge leakage. The hysteresis in the output and transfer characteristics and shifts in the threshold voltage of the transfer characteristics were attributed to the charging and discharging of the floating gate. Fast switching and large memory windows (∼26 V) exhibiting high charge density (6.25 × 1012 cm−2) were achieved.

Microwave method for high-frequency properties of graphene

Abstract: Graphene is a remarkable material, which is yet to make the transition from unique laboratory phenomenon to useful industrial material. One missing element in the development process is a quick method of quality control of the electrical properties of graphene which may be applied in, or close to, the graphene growth process on an industrial scale. In this study, the authors describe a non-contact method using microwave resonance which potentially solves this problem. They describe the technique, consider its limitations and accuracy and suggest how the method may have future take up.

High-speed energy-efficient bi-directional transceiver for on-chip global interconnects

Abstract: In this paper, a new bi-directional transceiver has been proposed for high-speed signalling across on-chip global interconnects. The proposed transceiver has two modes of operation namely, the transmitter and the receiver. As a result, two transceivers sitting at the two ends of an interconnect can support two-way communication through the same link. The transceiver has very low small-signal impedance for both modes of operation and thereby supports high bandwidth of the link. Moreover, because of its high transimpedance gain over a large bandwidth in the receiving mode, the signalling current can be reduced to a very low value. The circuit has been designed in 65 nm, 1.2 V process with a global interconnect of length 10 mm and width 1.5 μm. Post-layout simulation of the transceivers with the link gives an energy efficiency of 0.101 pJ/b for a data transmission of 14 Gbps.

Origin of 1/f noise in graphene produced for large-scale applications in electronics

Abstract: The authors report a detailed investigation of the flicker noise (1/f noise) in graphene films obtained from chemical vapour deposition (CVD) and chemical reduction of graphene oxide. The authors find that in the case of polycrystalline graphene films grown by CVD, the grain boundaries and other structural defects are the dominant source of noise by acting as charged trap centres resulting in huge increase in noise as compared with that of exfoliated graphene. A study of the kinetics of defects in hydrazine-reduced graphene oxide (RGO) films as a function of the extent of reduction showed that for longer hydrazine treatment time strong localised crystal defects are introduced in RGO, whereas the RGO with shorter hydrazine treatment showed the presence of large number of mobile defects leading to higher noise amplitude.

High gain two-stage amplifier with positive capacitive feedback compensation

Abstract: A novel topology for a high gain two-stage amplifier is proposed. The proposed circuit is designed in a way that the non-dominant pole is at output of the first stage. A positive capacitive feedback around the second stage introduces a left half-plane zero, which cancels the phase shift introduced by the non-dominant pole, considerably. The dominant pole is at the output node, which means that increasing the load capacitance has minimal effect on stability. Moreover, a simple and effective method is proposed to enhance slew rate. Simulation shows that slew rate is improved by a factor of 2.44 using the proposed method. The proposed amplifier is designed in a 0.18 μm complementary metal-oxide-semiconductor process. It consumes 0.86 mW power from a 1.8 V power supply and occupies 3038.5 μm 2 of chip area. The DC gain is 82.7 dB and gain bandwidth (GBW) is 88.9 MHz when driving a 5 pF capacitive load. Also low frequency common-mode rejection ratio and positive power supply rejection ratio are 127 and 83.2 dB, respectively. They are 24.8 and 24.2 dB at GBW frequency, which are relatively high and are other important properties of the proposed amplifier. Moreover, simulations show convenient performance of the circuit in process corners and also the presence of a mismatch.

Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic

Abstract: In this paper, a new voltage mirror circuit by using carbon nanotubes (CNTs) technology is presented. This circuit is specifically proposed for the application of duplicating multiple-valued and fuzzy dynamic random access memories. The given structure prevents any voltage drop for the capacitor inside the memory cell. As a result, any fanout circuit can be driven. The new structure can be utilised for different multiple-valued logic systems without a change. The unique characteristics of carbon nanotube field effect transistor (CNFET) technology are exploited in this paper to meet the desired design goals. It demonstrates the potentials of CNFET technology in a realistic very large-scale integration application. The proposed design is highly tolerant to D CNT variation and it is also immune to misaligned CNTs. Simulation results demonstrate that it provides sufficient driving capability with reasonable accuracy.

Conversion of polypropylene to two-dimensional graphene, one-dimensional carbon nano tubes and zero-dimensional C-dots, all exhibiting typical sp2-hexagonal carbon rings

Abstract: For the first time single precursor, polypropylene (PP) has been used to synthesise two-dimensional (2D) graphene, 1D carbon nanotubes (CNT) and 0D carbon dots (C-dots). The carbon chains of PP polymer contain tertiary carbon atoms that have considerably lower resistance against degradation and cracking which is easy at low activation energy. Thermal cracking of PP was used for the synthesis of 2D graphene, 1D CNT and 0D C-dots materials. Although the basic structure of all three materials is same, that is, having hexagonal lattice of carbon, they show different properties. Morphology of these carbon materials was characterised by scanning electron microscopy, transmission electron microscopy and properties along with sp2 and sp3 content were analysed by ultra-violet–visible spectroscopy, X-ray diffraction (XRD) and Raman spectroscopy. It was observed with the help of Raman and XRD that as the dimensionalities of hexagonal carbon decreases there is an increase in defects, for example, graphene synthesised from PP showed negligible defects, CNT had considerable disorderness, whereas 0D C-dots showed maximum disorderness. This could be the reason for scientists turning from CNT to graphene as future material for its application in electrical and electronic fields, nevertheless, only time will tell whether graphene can be the answer as currently being thought of.

Subquadratic space complexity Gaussian normal basis multipliers over GF (2 m ) based on Dickson–Karatsuba decomposition

Abstract: Gaussian normal basis (GNB) of the even-type is popularly used in elliptic curve cryptosystems. Efficient GNB multipliers could be realised by Toeplitz matrix-vector decomposition to realise subquadratic space complexity architectures. In this study, Dickson polynomial representation is proposed as an alternative way to represent an GNB of characteristic two. The authors have derived a novel recursive Dickson–Karatsuba decomposition to achieve a subquadratic space-complexity parallel GNB multiplier. By theoretical analysis, it is shown that the proposed subquadratic multiplier saves about 50% bit-multiplications compared with the corresponding subquadratic GNB multiplication using Toeplitz matrix-vector product approach.