Showing papers in "Microelectronics Reliability in 1999"

TL;DR: In this article, the electromigration performance of Cu metalization has been reviewed with an explanation as to why the advantage of Cu over Al alloys in the fine line regime is not as great as anticipated.

TL;DR: In this article, the potential of these technologies to enhance module reliability and lifetime through a power cycling test is assessed through failure analysis results and the failure mechanisms related to each technology are explained in detail.

TL;DR: In this paper, a viscoplastic constitutive model was used to analyze the thermally induced plastic and creep deformation and low cycle fatigue behavior of the solder joints in Chip Scale Packages (CSP) mounted on Printed Circuit Boards (PCB).

TL;DR: In this article, the effect of molding compound and die attach film on package warpage and solder joint reliability was investigated, and it was found that the mold compound tremendously affected the solder joints reliability.

TL;DR: In this article, the influence of temperature on semiconductor device characteristics is discussed with regard to physical limits for device operation, and an overview of the state-of-the-art of high-temperature devices is given.

TL;DR: In this article, the authors investigated the dielectric, structural and electric properties of tantalum pentoxide thin films on Si prepared by two conventional for modern microelectronics methods (RF sputtering of Ta in Ar + O2 mixture and thermal oxidation of Tantalum layer on Si) and found that the formation of ultra thin SiO2 film at the interface with Si, during fabrication implementing the methods used, is unavoidable as both, X-ray photoelectron spectroscopy and electrical measurements.

TL;DR: In this paper, the role of surface contaminants, especially ionic types, may have significant influences on the overall process of electrochemical migration in metal resistive short-circuits.

TL;DR: In this paper, thermal-induced voltage alteration (TIVA) and seebeck effect imaging (SEI) are used to localize shorted and open conductors from the front and backside of an IC.

TL;DR: In this paper, a degradation study of high-brightness Nichia single-quantum well AlGaN/InGaN /GaN green light-emitting diodes (LEDs) was performed.

TL;DR: In this article, the authors reviewed the current status of reliability issues in III-V optical devices, semiconductor lasers and light emitting diodes, and GaAs-based heterojunction bipolar transistors (HBTs).

TL;DR: In this article, the rotational frequency dependence on median cycles to failure was investigated on surface micromachined microengines driving load gears to determine the rotation frequency dependence of rotational joints.

TL;DR: In this article, a slow-trap profiling technique was used to characterise silicon-based MOS capacitors in strong inversion and showed that NO nitridation eliminates while N2O creates defects acting as slow traps in both Si and SiC substrates.

TL;DR: In this article, the reliability of IGBT power modules with respect to the metallized ceramic (substrate) and the solder layer between the substrate and copper baseplate was investigated.

TL;DR: In this article, an investigation of O2, Ar and Ar/H2 plasma cleaning was carried out on plastic ball grid array (PBGA) substrates to study its effects on surface cleanliness, wire bondability and molding compound/solder mask adhesion.

TL;DR: In this article, a pulsed laser system dedicated to the simulation of radiation effects on integrated circuits is presented, and two SPICE models of radiation induced transient currents are proposed to be used for results analysis.

TL;DR: The triggering of grounded-gate nMOS transistors and field-oxide devices, essential for optimized protection design, is addressed by transmission line pulser (TLP)-pulsed emission microscopy as discussed by the authors.

TL;DR: In this paper, the Ni-rich phases in the depleted junction region played the role of trapping and recombination centers to generate the leakage currents and that the leakage current was generated by thermionic field emission.

TL;DR: In this article, NMOS transistors stacked in a cascode configuration provide robust ESD protection for mixed voltage I / O in both silicided and silicide-blocked technologies.

TL;DR: In this paper, structural and electrical properties of amorphous and crystalline Ta 2 O 5 thin films deposited on p-type Si by low pressure metalorganic chemical vapour deposition from a Ta(OC 2 H 5 ) 5 source have been investigated.

TL;DR: In this article, the authors proposed a new cluster index that utilizes the defect location data on a wafer in terms of the coefficient of variation, which is independent of the chip area and does not require assumptions on the distribution of defects.

TL;DR: In this paper, the stud bumping of gold, palladium, and solder is described and also a novel bumping approach for fine pitch solder deposition down to 100 μm pitches using thermosonic bonding on a modified wedge-wedge bonding machine.

TL;DR: The IDS 2000 tool as discussed by the authors is a fully integrated circuit timing analysis tool that provides measurements of electrical waveforms by direct access to the diffusion nodes through the backside of CMOS integrated circuits.

TL;DR: In this article, a study on the solder joint mechanical reliability evaluation of two grid array packages: a micro land grid array (μLGA) and a micro ball grid array for mobile phones is presented.

TL;DR: In this article, the reliability of ball grid arrays (BGAs) was evaluated with special emphasis on space applications and the most critical variables incorporated in this experiment were package type, board material, surface finish, solder volume, and environmental condition.

TL;DR: In this article, the main factors influencing yield and the relationship between yield and reliability of the final product are discussed, along with examples of their use and a simple model is given to demonstrate.

TL;DR: This work identifies and addresses failure modes common to a broad range of MEMS actuation systems, including adhesion (stiction) and friction-induced failures caused by improper operational methods, mechanical instabilities, and electrical instabilities.

TL;DR: In this article, the authors developed a testing rig for accelerated testing of a single chip under controlled pressure conditions and created a thermomechanical simulation of the chip/testing rig assembly for the determination of internal stresses and strains due to actual operation.

TL;DR: In this paper, the authors present a physics-of-failure process to identify, induce and analyze failure mechanisms causing intermittent failures, high warranty returns and cannot duplicate (CND) problems of the digital electronic cruise control module (CCM).

TL;DR: In this article, the authors derived design rules for maximum current handling capability of gold bond wires based on two failure mechanisms: (1) fusing of the wire; and (2) degradation of the interface between gold bond balls and the aluminum bond pads under high current/high temperature stress.