A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application

TLDR: Current mode logic based novel 2:1 multiplexer featuring dual latch to be steered by either CLK or CLKBAR, simulated for 90nm CMOS technology using Cadence Virtuoso platform at a power supply of 1Volt with 10GHz switching frequency.

Abstract: As the high speed electronic systems are in the midway of getting shifted from conventional parallel data transmission to new high data rate serial link, design of an unit cell (i.e. MUX) for the serializer interface has become an area of interest. In this paper, we have demonstrated current mode logic based novel 2:1 multiplexer featuring dual latch to be steered by either CLK or CLKBAR. The new design approach is simulated for 90nm CMOS technology using Cadence Virtuoso platform at a power supply of 1Volt with 10GHz switching frequency. The main noted point of this circuit is that it generates a massive output swing of 955mV (95.5% of the power supply) and outsmarted the prior arts by offering an average power and delay of 61.02μW and 32.93ps respectively. The robustness of the architecture is tested in different process corners with 'no skew' and '5% process skew' through 200 runs of Monte-Carlo. The energy/bit, RMS Jitter, PP Jitter and BER of the proposed design read a value of 1.74fJ, 4.41ps, 15.01ps and