Proceedings ArticleDOI
A fast locking charge-pump PLL with adaptive bandwidth
Yan Ge,Wennan Feng,Zhongjian Chen,Song Jia,Lijiu Ji +4 more
- Vol. 1, pp 383-386
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TLDR
Design of bandwidth adaptive phase-locked loops (PLL) to achieve fast locking is presented and the measured results show that the experimental chip has properties of fast locking less than 4 mus and low power consumption about 18mW.Abstract:
Design of bandwidth adaptive phase-locked loops (PLL) to achieve fast locking is presented in this paper. The proposed topology uses only one adaptive phase frequency detector (PFD) and controllable charge pumps to realize adaptive bandwidth scheme. With a SMIC standard 0.25mum 1P5M 2.5V CMOS logic process, the measured results show that the experimental chip has properties of fast locking less than 4 mus and low power consumption about 18mWread more
Citations
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Dissertation
Analysis and design of high order digital phase locked loops
TL;DR: This thesis presents a new design technique for high order Digital PLL (DPLL) systems with a charge pump phase frequency detector component, offering an alternative to the common design practice which is to analyze the DPLL using a linearised model of the analogue PLL.
Dissertation
Conception orientée délai : étude, développement et réalisation d’une boucle à verrouillage de phase large bande stabilisée par une boucle à verrouillage de délai
TL;DR: In this article, a new technique for stabilisation, issue de la superposition d'une boucle a verrouillage de delai and de phase, is proposed.
Rigorous Stability Criterion for Digital Phase Locked Loops
Brian Daniels,Ronan Farrell +1 more
TL;DR: In this paper, the authors proposed a rigorous stability criterion for an arbitrary order digital phase locked loop (DPLL), with a charge pump phase frequency detector (CP-PFD) component.
Proceedings ArticleDOI
An fast lock technique for wide band PLL frequency synthesizer design
Ko-Chi Kuo,Chi-Wei Wu +1 more
TL;DR: In this paper, a fast phase frequency detector charge pump (Fast-PFDCP) was used to enhance the locking speed of the proposed PLL, which can be used for IEEE 802.1 1ac unlicensed band of Wi-Fi with the frequency ranged from 4.39 GHz to 5.71 GHz.
Proceedings ArticleDOI
Design of the Fast Acquisition PLL with Wide Tuning Range
TL;DR: This paper presents a design of adaptive gain phase-locked loop (PLL) which features fast acquisition, low jitter and wide tuning range, and a dual-edge-triggered phase frequency detector and a self-regulated voltage controlled oscillator are employed.
References
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Book
Phase-locked loops : design, simulation, and applications
TL;DR: This chapter discusses the design procedure for Mixed-Signal PLLs, and the PLL in Communications, and discusses the Pull-in Process and the Laplace Transform.
Journal ArticleDOI
Charge-Pump Phase-Lock Loops
TL;DR: This paper analyzes typical charge-pump circuits, identifies salient features, and provides equations and graphs for the design engineer.
Journal ArticleDOI
A CMOS self-calibrating frequency synthesizer
TL;DR: In this article, a programmable phase-locked-loop (PLL)-based frequency synthesizer, capable of automatically adjusting the nominal center frequency of the VCO to an optimum value is described.
Journal ArticleDOI
A simple precharged CMOS phase frequency detector
TL;DR: In this paper, a simple precharged CMOS phase frequency detector (PFD) was proposed, which works up to clock frequencies of 800 MHz according to SPICE simulations on the extracted layout.
Journal ArticleDOI
Time resolution of NMOS sampling switches used on low-swing signals
H.O. Johansson,Christer Svensson +1 more
TL;DR: An expression for the aperture time for an NMOS switch when the input has low swing is presented, which shows that the maximum theoretical time resolution for a switch in 0.8-/spl mu/m standard CMOS is 21 ps /spl sim/48 Gb/s.