Proceedings ArticleDOI
A method to derive compact test sets for path delay faults in combinational circuits
J. Saxena,Dhiraj K. Pradhan +1 more
- pp 724-733
TLDR
A technique to derive maximal compatible path delay fault sets by using the notion of compatible faults is described, based on identifying necessary conditions on lines in a circuit along with values a line cannot take in order to test a given path.Abstract:
In path delay fault testing, the number of faults to be tested in a circuit is inherently very large. Therefore, deriving compact test sets for path delay faults is an important issue. This paper presents a method to derive compact test sets for path delay faults by using the notion of compatible faults. A technique to derive maximal compatible path delay fault sets is described. The technique is based on identifying necessary conditions on lines in a circuit along with values a line cannot take in order to test a given path. Experimental results on ISCAS benchmarks are presented to demonstrate the effectiveness of using this technique in reducing test set size. >read more
Citations
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Proceedings ArticleDOI
Logic soft errors in sub-65nm technologies design and CAD challenges
TL;DR: Effective logic soft error protection requires solutions to the following three problems: accurate soft error rate estimation for combinational logic networks; automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected.
Proceedings ArticleDOI
Three-pattern tests for delay faults
P. Franco,Edward J. McCluskey +1 more
TL;DR: It is shown that accurate delay models are needed for effective delay fault testing, particularly important for large timing optimized circuits with many paths.
Proceedings ArticleDOI
Dynamic Compaction for High Quality Delay Test
Zheng Wang,Duncan M. Walker +1 more
TL;DR: Experimental results for ISCAS89 benchmark circuits and two industry circuits show that the pattern count of KLPG can be significantly reduced (up to 3x compared to static compaction) using the proposed method.
Journal ArticleDOI
Function-based compact test pattern generation for path delay faults
TL;DR: A function-based nonenumerative automatic test pattern generation (ATPG) methodology for detecting path delay faults (PDFs) consisting of a number of topological circuit traversals during each a linear number of Boolean functions is generated per circuit line.
Journal ArticleDOI
Test enrichment for path delay faults using multiple sets of target faults
I. Pomeranz,Sudhakar M. Reddy +1 more
TL;DR: An improved approach is developed which applies this technique at deeper levels of hierarchy, so that effective tests can be bedeveloped for large designs with complex submodules.
References
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Journal ArticleDOI
On Delay Fault Testing in Logic Circuits
Chin Jen Lin,Sudhakar M. Reddy +1 more
TL;DR: Algorithms, based on a five-valued logic system, to accurately calculate the detection probability of path delay faults by random delay tests as well as to derive deterministic tests to detect pathdelay faults are proposed.
Journal ArticleDOI
On path selection in combinational logic circuits
TL;DR: Algorithms to select such sets of paths with minimum cardinality that includes at least one path, with maximum modeled delay, for each circuit lead or gate input are given.
Proceedings ArticleDOI
Advanced automatic test pattern generation techniques for path delay faults
M.H. Schulz,K. Fuchs,F. Fink +2 more
TL;DR: The authors propose a ten-valued logic and describe the corresponding implication and path sensitization procedures in detail and discuss an extended multiple backtrace procedure, which has been developed specifically to meet the requirements of path delay testing.