A methodology for designing LVDS interface system
01 Dec 2016-pp 284-288
TL;DR: A complete transmitter has been designed using low-voltage differential signaling (LVDS) technology, a new analog technology based on the serial I/O interface data communications, which helps to improve the performance of transmitter and reducing electrostatic discharge issues.
Abstract: In this paper, a complete transmitter has been designed using low-voltage differential signaling (LVDS) technology. It is a new analog technology based on the serial I/O interface data communications. The complete transmitter circuit consists of driver, cascode current mirror circuit, pseudo random binary sequence (PRBS), and electrostatic discharge (ESD) pad. Here, transmitter is designed initially, and its biasing has been done using cascode current mirror. The layout parameter variation approach has been used to design ESD protection circuit for transmitter. An effort was made to reduce the parasitic capacitance and parasitic resistance. It helps to improve the performance of transmitter and reducing electrostatic discharge issues. The complete system has been designed using 0.18 μm CMOS technology at 1.8 V. The data rate of 2 Gbps and power consumption of 6.3 mW has been achieved using Cadence virtuoso PDK of Silatera Malaysia.
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TL;DR: In this article, a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface was presented, which was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator.
Abstract: This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 ps@2.5 Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.
3 citations
Cites background from "A methodology for designing LVDS in..."
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TL;DR: A significant reduction in power dissipation is achieved by selecting a proper sizing of transistor and using differential signaling technique of the data transmission.
Abstract: In this paper, a novel global interconnect low voltage differential signaling (LVDS) transmitter for network-on-chip (NOC) has been proposed to achieve less global interconnect delay and low power dissipation. The proposed interconnect with transmitter has been examined in two different conditions, without buffer and with buffer in between interconnect and also impact of feature size scaling has been analyzed. The performance has been analyzed for the NOC interconnect with $0.350 \mu \mathrm {m}$ and $0.180 \mu \mathrm {m}$ CMOS technology. On scaling the technology with $0.350 \mu \mathrm {m}$ to $0.180 \mu \mathrm {m}$, the results show 15.68% global interconnect delay reduce for transmitter without buffer (Model-I) in between interconnect and with buffer (Model-II) global interconnect delay reduction of 15.83%. A significant reduction in power dissipation is achieved by selecting a proper sizing of transistor and using differential signaling technique of the data transmission. The power dissipation in $0.350 \mu \mathrm {m}$ technology is $1.78 \mathrm {m}\mathrm {W}$ and $0.180 \mu \mathrm {m}$ technology is $2.1929 \mathrm {m}\mathrm {W}$, respectively, at data rate of 2.9 Gbps and 3.5 Gbps at different technology for two different models.
3 citations
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TL;DR: In this paper, a hybrid of mesh-ring with partial diagonal link (HMRPD) topology has been proposed for neuromorphic architectures, which has been examined in terms of average distance, hope count, and core count of application from source to destination.
Abstract: An emerging neural network consists of larger core chips that rely on the network-on-chip (NoC) based interconnection to control the massive volume of inter-neuron traffic. The NoC interconnect renders high flexibility as it solves one of the critical challenges of reconfigurable neural-networks in hardware implementation. In this paper, a novel two-dimensional (2-D) hybrid of mesh-ring with partial diagonal link (HMRPD) topology has been proposed for neuromorphic architectures. The proposed architecture has been examined in terms of average distance, hope count, and core count of application from source to destination. The analysis shows that the proposed HMRPD topology has low communication costs, high scalable due to small diameter, average distance, and high bandwidth. Finally, a comparison has been performed with the existing topology for neural-network hardware accelerators. Moreover, the proposed HMRPD topology reduces latency and improves the throughput of neural information processing.
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References
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TL;DR: A 4-Gb/s I/O circuit that fits in 0.1-mm/sup 2/ of die area, dissipates 90 mW of power, and operates over 1 m of 7-mil 0.5-oz PCB trace in a 0.25-/spl mu/m CMOS technology is presented.
Abstract: We present a 4-Gb/s I/O circuit that fits in 0.1-mm/sup 2/ of die area, dissipates 90 mW of power, and operates over 1 m of 7-mil 0.5-oz PCB trace in a 0.25-/spl mu/m CMOS technology. Swing reduction is used in an input-multiplexed transmitter to provide most of the speed advantage of an output-multiplexed architecture with significantly lower power and area. A delay-locked loop (DLL) using a supply-regulated inverter delay line gives very low jitter at a fraction of the power of a source-coupled delay line-based DLL. Receiver capacitive offset trimming decreases the minimum resolvable swing to 8 mV, greatly reducing the transmission energy without affecting the performance of the receive amplifier. These circuit techniques enable a high level of I/O integration to relieve the pin bandwidth bottleneck of modern VLSI chips.
241 citations
"A methodology for designing LVDS in..." refers background in this paper
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TL;DR: The design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard are presented.
Abstract: This paper presents the design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard. Due to the differential transmission technique and the low voltage swing, LVDS allows high transmission speeds and low power consumption at the same time. In the proposed transmitter, the required tolerance on the dc output levels was achieved over process, temperature, and supply voltage variations with neither external components nor trimming procedures, by means of a closed-loop control circuit and an internal voltage reference. The proposed receiver implements a dual-gain-stage folded-cascode architecture which allows a 1.2-Gb/s transmission speed with the minimum common-mode and differential voltage at the input. The circuits were implemented in a 3.3-V 0.35-/spl mu/m CMOS technology in a couple of test chips. Transmission operations up to 1.2 Gb/s with random data patterns and up to 2 Gb/s in asynchronous mode were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 43 and 33 mW, respectively.
203 citations
"A methodology for designing LVDS in..." refers background in this paper
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TL;DR: In this article, two lowvoltage low-power LVDS drivers for high-speed point-to-point links are discussed, which can operate at data rates up to gigabits per second.
Abstract: Two low-voltage low-power LVDS drivers used for high-speed point-to-point links are discussed. While the previously reported LVDS drivers cannot operate with low-voltage supplies, the proposed double current sources (DCS) LVDS driver and the switchable current sources (SCS) LVDS driver are suitable for low-voltage applications. Although static current consumption is greater than the minimum amount required by the signal swing, the DCS LVDS driver is simple and fast. The SCS LVDS driver, by dynamically switching the current sources, draws minimum static current and reduces the power consumption by 60% compared to previously reported realizations. Both drivers were fabricated in a standard 0.35-/spl mu/m CMOS process; they are compliant with LVDS standards and can operate at data rates up to gigabits-per-second.
130 citations
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TL;DR: The design and the implementation of input-output (I/O) interface circuits for serial data links in the gigabit-per-second range are described and the output levels are within the 100K tolerance over the full range of process, supply voltage, and temperature (PVT) variations without resorting to external components or on-chip trimming.
Abstract: This paper describes the design and the implementation of input-output (I/O) interface circuits for serial data links in the gigabit-per-second range. The cells were implemented in a 3.3-V 0.35-/spl mu/m CMOS technology in a couple of test chips. The transmitter is fully compatible (DC coupling) with 100K positive emitter-coupled logic (PECL) systems and it is based on the voltage-switching principle in order to allow different termination schemes besides the canonical ECL termination, i.e., 50-/spl Omega/ toward (V/sub DD/-2) V. The addition of some circuit techniques such as dynamic biasing and strobed current switching boosts the dynamic performance of the basic voltage-switching scheme and relaxes the requirements for a high bias current and large-size output devices at the same time. Moreover, thanks to the developed reference circuit, using both feedforward and feedback controls, the output levels are within the 100K tolerance over the full range of process, supply voltage, and temperature (PVT) variations without resorting to external components or on-chip trimming. The receiver cell is based on a complementary-differential architecture providing high speed and low error on the duty cycle of the CMOS output signal. The integrated receiver-transmitter chain exhibits a maximum toggle frequency of 1 GHz, while a chip-to-chip transmission link using the developed I/O interface was tested up to 1.2 Gb/s.
9 citations
"A methodology for designing LVDS in..." refers background in this paper
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TL;DR: This work proposes novel methodology which describes the optimized design prediction of ESD protection device under HBM (Human Body Model) stress condition and shows that spacing optimization effectively elevates It2 by increasing the ballasting behavior and uniformity in current distribution while causing only a marginal increment in parasitic capacitance.
Abstract: This work explores the new ESD (electrostatic discharge) protection design methodology for high speed off-chip communication ICs (Integrated Circuits). We propose novel methodology which describes the optimized design prediction of ESD protection device under HBM (Human Body Model) stress condition. Furthermore, we have discussed the ESD-I/O circuit interaction and improved the ESD circuit robustness by varying the various layout parameters and minimizing the parasitic capacitance of the protection device. Here, GG-NMOS (Gate Grounded NMOS) is taken as an ESD protection device. Moreover, LVDS (Low Voltage Differential Signaling) driver circuit is used as test circuit, where we compared the impact of capacitance due to protection device on circuit performance. The second breakdown triggering current (It2) which can be considered a metric of ESD robustness, is dependent on the drain to gate contact spacing (DCGS). We show that spacing optimization effectively elevates It2 by increasing the ballasting behavior and uniformity in current distribution while causing only a marginal increment in parasitic capacitance.
2 citations
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