Proceedings ArticleDOI
A methodology for designing LVDS interface system
Jayshree,Seema Verma,Amitabh Chatterjee +2 more
- pp 284-288
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TLDR
A complete transmitter has been designed using low-voltage differential signaling (LVDS) technology, a new analog technology based on the serial I/O interface data communications, which helps to improve the performance of transmitter and reducing electrostatic discharge issues.Abstract:
In this paper, a complete transmitter has been designed using low-voltage differential signaling (LVDS) technology. It is a new analog technology based on the serial I/O interface data communications. The complete transmitter circuit consists of driver, cascode current mirror circuit, pseudo random binary sequence (PRBS), and electrostatic discharge (ESD) pad. Here, transmitter is designed initially, and its biasing has been done using cascode current mirror. The layout parameter variation approach has been used to design ESD protection circuit for transmitter. An effort was made to reduce the parasitic capacitance and parasitic resistance. It helps to improve the performance of transmitter and reducing electrostatic discharge issues. The complete system has been designed using 0.18 μm CMOS technology at 1.8 V. The data rate of 2 Gbps and power consumption of 6.3 mW has been achieved using Cadence virtuoso PDK of Silatera Malaysia.read more
Citations
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Journal ArticleDOI
A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology
TL;DR: In this article, a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface was presented, which was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator.
Proceedings ArticleDOI
Design and Analysis of Novel Interconnects with Network-on-Chip LVDS Transmitter for Low Delay
Jayshree,G. Seetharaman +1 more
TL;DR: A significant reduction in power dissipation is achieved by selecting a proper sizing of transistor and using differential signaling technique of the data transmission.
Proceedings ArticleDOI
Design of High Performance HMRPD Network on Chip Interconnect for Neuromorphic Architectures
TL;DR: In this paper, a hybrid of mesh-ring with partial diagonal link (HMRPD) topology has been proposed for neuromorphic architectures, which has been examined in terms of average distance, hope count, and core count of application from source to destination.
Journal ArticleDOI
Design and Area Performance Energy Consumption Comparison of Secured Network-on-Chip with PTP and Bus Interconnections
TL;DR: A dynamic adaptive (DyAD) routing algorithm has been proposed, which works based on congestion information in the path, and shows that NoC-BI scales quite strongly, and results are encouraging for various metrics compared to PTP-BI and AXI4-BBI.
References
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Journal ArticleDOI
Low-power area-efficient high-speed I/O circuit techniques
TL;DR: A 4-Gb/s I/O circuit that fits in 0.1-mm/sup 2/ of die area, dissipates 90 mW of power, and operates over 1 m of 7-mil 0.5-oz PCB trace in a 0.25-/spl mu/m CMOS technology is presented.
Journal ArticleDOI
LVDS I/O interface for Gb/s-per-pin operation in 0.35-/spl mu/m CMOS
TL;DR: The design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard are presented.
Journal ArticleDOI
Low-voltage low-power LVDS drivers
TL;DR: In this article, two lowvoltage low-power LVDS drivers for high-speed point-to-point links are discussed, which can operate at data rates up to gigabits per second.
Journal ArticleDOI
1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-/spl mu/m CMOS
TL;DR: The design and the implementation of input-output (I/O) interface circuits for serial data links in the gigabit-per-second range are described and the output levels are within the 100K tolerance over the full range of process, supply voltage, and temperature (PVT) variations without resorting to external components or on-chip trimming.
Proceedings ArticleDOI
A Novel Co-design Methodology for Optimizing ESD Protection Device Using Layout Level Approach
TL;DR: This work proposes novel methodology which describes the optimized design prediction of ESD protection device under HBM (Human Body Model) stress condition and shows that spacing optimization effectively elevates It2 by increasing the ballasting behavior and uniformity in current distribution while causing only a marginal increment in parasitic capacitance.