Proceedings ArticleDOI
A non-sequential phase detector for PLL-based high-speed data/clock recovery
Yonghui Tang,Randall L. Geiger +1 more
- Vol. 1, pp 428-431
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TLDR
A new Phase Detector (PD) that can be used for high-speed random data/clock recovery is presented that exploits the leading and lagging signals from the VCO which greatly simplifies the PD structure.Abstract:
The Phase-Locked Loop (PLL) is a widely used block in data and clock recovery circuits. Phase detectors form a crucial part of the PLL. The requirements for phase detectors used in random data recovery are more stringent than the one used for clock recovery, especially at high-speed. This paper presents a new Phase Detector (PD) that can be used for high-speed random data/clock recovery. In contrast to most existing structures which are speed-limited by sequential logic circuits, it exploits the leading and lagging signals from the VCO which greatly simplifies the PD structure. Using the HSPICE simulator and HP 0.35 u standard CMOS process models, simulation results show that the PD can operate at 2 GHz over the 0/spl deg/C to 100/spl deg/C temperature range and over fast and slow process corners.read more
Citations
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Proceedings ArticleDOI
Segmentation of 3D MR Liver Images Using Synchronised Oscillators Network
TL;DR: A segmentation method based on three-dimensional network of synchronized oscillators applied for 3D MR liver images is presented, demonstrating its resistance to changes of visual image information caused for example by noise, very often present in biomedical images.
Patent
Phase-locked loop with loop select signal based switching between frequency detection and phase detection
TL;DR: In this article, a phase-locked loop (PLL) is defined as a dual-loop PLL with the first and second loops corresponding to respective frequency and phase loops, and the loop selection circuitry is configured such that the loop select signal as applied to a control input of a current-generating component of the first loop represents a delayed and inverted version of the loop-select signal.
Proceedings ArticleDOI
Design of low power and high speed phase detector
Nitin Kumar,Manoj Kumar +1 more
TL;DR: A new PFD design in 0.18μm CMOS technology using 3T XOR and 3T NAND gates is presented and shows less power consumption than conventional MOS current mode logic design.
Proceedings ArticleDOI
A novel configurable no dead-zone digital phase detector design
TL;DR: A novel configurable no dead-zone digital phase detector is proposed in this paper, which can be part of a standard digital cell library and can easily be used in field programmable gate array (FPGA).
References
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R. Zimmermann,Wolfgang Fichtner +1 more
TL;DR: This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.
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Charge-Pump Phase-Lock Loops
TL;DR: This paper analyzes typical charge-pump circuits, identifies salient features, and provides equations and graphs for the design engineer.
Book
Monolithic phase-locked loops and clock recovery circuits : theory and design
TL;DR: In this article, a collection of 65 of the most important papers on phase-locked loops and clock recovery circuits is presented, with an extensive 40 page tutorial introduction and a comprehensive coverage of the field all in one self-contained volume.
Journal ArticleDOI
A self correcting clock recovery curcuit
TL;DR: A new approach to the problem of extracting clock from NRZ data is described, both simple and self correcting, that holds the clock in the center of the data eye.
Journal ArticleDOI
Clock recovery from random binary signals
TL;DR: A circuit for detecting timing errors between a binary signal and a local clock pulse generator and logical control signals for the clock are derived.