Proceedings ArticleDOI
A novel CMOS double-edge triggered flip-flop for low-power applications
Yu-Yin Sung,Robert Chen-Hao Chang +1 more
- Vol. 2, pp 665-668
Reads0
Chats0
TLDR
A novel low-power double-edge triggered flip-flop that uses a low-swing clock technology and low-Vt transistors for the clock transistors to reduce the leakage current problem.Abstract:
A novel low-power double-edge triggered flip-flop is presented in this paper. Low-power and high-speed flip-flops are required in many applications, especially in SoC systems. Double-edge triggered flip-flop can latch the data signal changes both from high to low and low to high. Thus, lower clock frequency is used while the data throughput is preserved. The proposed flip-flop uses a low-swing clock technology and low-Vt transistors for the clock transistors to reduce the leakage current problem. Beside, only a single latch is used and lower power consumption is achieved. HSPICE simulation results show that the power dissipation of the proposed flip-flop is reduced by at least 28% and the power-delay product is also reduced by at least 50%.read more
Citations
More filters
Journal ArticleDOI
Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop
TL;DR: The new technique employs a clock branch-sharing scheme to reduce the number of clocked transistors in the design and employs conditional discharge and split-path techniques to further reduce switching activity and short-circuit currents.
Journal ArticleDOI
A Fully Static True-Single-Phase-Clocked Dual-Edge-Triggered Flip-Flop for Near-Threshold Voltage Operation in IoT Applications
TL;DR: A fully static true-single-phase-clocked DET-FF is proposed to achieve reliable operation at voltages as low as a near-threshold regime and a True-Single-Phase-Clocking (TSPC) scheme is adopted to overcome clock overlap issues and enable low-power operation.
Quaternary Sequential Circuits
TL;DR: In this article, a 4-bit counter using multiple-valued D flip-flops is presented, which is built by three input NMIN gates and has both preset and clear inputs.
Proceedings ArticleDOI
A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop
TL;DR: This paper has reviewed several earlier designs of double-edge triggered flip-flops and presented an 8-bit low power shift register by using a newly designed DETFF, taking advantage of two parallel data paths that work in opposite phases of the single clock without an inverted input trigger.
Proceedings ArticleDOI
Engery-Efficient Double-Edge Triggered Flip-Flop Design
TL;DR: The proposed DETFF fully utilizes the multi-V th scheme provided by advanced CMOS processes without paying the price of large area, slow clocking frequency, and poor noise immunity.
References
More filters
Journal ArticleDOI
A reduced clock-swing flip-flop (RCSFF) for 63% power reduction
TL;DR: A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip- flop which embodies the leakage current cutoff mechanism.
Journal ArticleDOI
A low-swing clock double-edge triggered flip-flop
Chulwoo Kim,Sung-Mo Kang +1 more
TL;DR: A low-swing clock double-edge triggered flip-flop (LSDBF) is developed to reduce power consumption significantly compared to conventional FFs and avoids unnecessary internal node transition and reduces conflicting currents.
Proceedings ArticleDOI
A Reduced Clock-swing Flip-flop (RCSFF) For 63% Clock Power Reduction
Kawaguchi,Sakurai +1 more
TL;DR: A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip- flop which embodies the leak current cutoff mechanism.
Journal ArticleDOI
A novel CMOS implementation of double-edge-triggered flip-flops
S.-L.L. Lu,Milos D. Ercegovac +1 more
TL;DR: A CMOS implementation of a D-type double-edge-triggered flip-flop (DET-FF) is presented, which has advantages with respect to both system speed and power dissipation.
Proceedings ArticleDOI
A single latch, high speed double-edge triggered flip-flop (DETFF)
Troy A. Johnson,I.S. Kourtev +1 more
TL;DR: This paper describes an original circuit design of a static CMOS double-edge triggered flip-flop (DETFF) that has fewer transistors than other published staticCMOS DETFFs and performs favorably when compared to existing static CMos DETFF circuits.