Proceedings ArticleDOI
A simulation-based approach to test pattern generation for synchronous sequential circuits
Paolo Camurati,Fulvio Corno,Paolo Prinetto,M. Sonza Reorda +3 more
- pp 263-267
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TLDR
The authors present SETA, a sequential test generator based on automata, an ATPG applicable to synchronous circuits working in the fundamental mode, and state-of-the-art simulation techniques used to yield satisfactory experimental results on the ISCAS89 benchmark set.Abstract:
Particular design environments, e.g., those based on partial scan, may prevent design for testability techniques from reducing testing to a combinational problem: ATPG for sequential devices thus remains a challenge. Random and deterministic structure-oriented techniques are state-of-the-art, but there is a growing interest in methods that resort to the automaton of the circuit. The authors present SETA, a sequential test generator based on automata, an ATPG applicable to synchronous circuits working in the fundamental mode. SETA generates test patterns while trying to disprove the equivalence of two automata. SETA is simulation-based: within the theoretical framework of the product machine, state-of-the-art simulation techniques are used to yield satisfactory experimental results on the ISCAS89 benchmark set. >read more
Citations
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Journal ArticleDOI
GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits
TL;DR: A prototype system named GATTO is used to assess the effectiveness of the approach in terms of result quality and CPU time requirements and the results are the best ones reported in the literature for most of the largest standard benchmark circuits.
Proceedings ArticleDOI
A genetic algorithm for automatic generation of test logic for digital circuits
TL;DR: This approach is the first attempt of exploiting evolutionary techniques for identifying the hardware for input pattern generation in BIST structures and shows that in most of the standard benchmark circuits the cellular automaton selected by the genetic algorithm is able to reach a fault coverage close to the maximum one.
Proceedings ArticleDOI
Diagnostic of path and gate delay faults in non-scan sequential circuits
TL;DR: A preliminary version of the proposed method for delay fault diagnosis for non-scan circuits based on path tracing through the sequential circuit, gate delay faults as well as path delay faults are considered and may be located in a faulty machine.
Proceedings ArticleDOI
Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs
TL;DR: An industrial case study for using defect injection and Spice simulation to generate defect oriented tests for the so-called strap defects in DRAMs, taking both the sensitivity of this defect to process variations and bit line coupling into consideration.
Proceedings ArticleDOI
Multiconfiguration technique to reduce test duration for sequential circuits
TL;DR: The DFT method the authors present is based on cycle breaking and sequential depth reduction guided by graph analysis, and an implementation of the method using scan flip-flops as modified instances is proposed.
References
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F. Brglez,D. Bryan,K. Kozminski +2 more
TL;DR: A set of 31 digital sequential circuits described at the gate level that extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-basedtest generation, and mixed sequential/scan-based test generation using partial scan techniques.
Book
Switching and Finite Automata Theory
Zvi Kohavi,Niraj K. Jha +1 more
TL;DR: Theories are made easier to understand with 200 illustrative examples, and students can test their understanding with over 350 end-of-chapter review questions.
Proceedings ArticleDOI
HITEC: a test generation package for sequential circuits
TL;DR: HITEC is presented, a sequential circuit test generation package to generate test patterns for sequential circuits, without assuming the use of scan techniques or a reset state, and several new techniques are introduced to improve the performance of test generation.
Journal ArticleDOI
Design for Testability—A Survey
TL;DR: The different techniques of design for testability are discussed in detail, including techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.