Open AccessProceedings Article
A Statistical Calculation of Fault Detection Probabilities By Fast Fault Simulation.
John A. Waicukauski,Eric Lindbloom,Edward B. Eichelberger,Donato O. Forlenza,Tim McCarthy +4 more
- pp 779-784
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This article is published in International Test Conference.The article was published on 1985-01-01 and is currently open access. It has received 42 citations till now. The article focuses on the topics: Fault coverage & Fault detection and isolation.read more
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Journal ArticleDOI
A method for generating weighted random test pattern
TL;DR: A new method for generating weighted random patterns for testing LSSD logic chips and modules and an algorithm for calculating an initial set of input-weighting factors and a procedure for obtaining complete stuck-fault coverage are presented.
Proceedings ArticleDOI
Constructive multi-phase test point insertion for scan-based BIST
N. Tamarapalli,Janusz Rajski +1 more
TL;DR: Experimental results demonstrate that complete or near-complete stuck-at fault coverage can be achieved by the proposed technique with the insertion of a few test points and a minimum number of phases.
Journal ArticleDOI
HSS--A High-Speed Simulator
TL;DR: The paper discusses the merits and drawbacks of the HSS strategy, the extensions of HSS to model sequential logic and the various applications of H SS, which include functional verification, design for testability, good machine signatures, and accurate simulation of transistor-level defects in certain CMOS technologies.
Journal ArticleDOI
On computing the sizes of detected delay faults
TL;DR: A model for delay faults that answers questions correctly, but with calculations simple enough to be done for large circuits, is presented.
Proceedings ArticleDOI
Fault Location with Current Monitoring
TL;DR: The proposed system combines a simple single fault model for test generation with a more realistic multiple defect model for diagnosis, and the associated hardware is sufficiently simple that on-board implementation is possible.