Journal ArticleDOI
Critical Path Tracing: An Alternative to Fault Simulation
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TLDR
Critical path tracing determines fault detection without explicit fault simulation, and appears to be a more efficient alternative to conventional methods.Abstract:
Critical path tracing determines fault detection without explicit. fault simulation. It appears to be a more efficient alternative to conventional methods.read more
Citations
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Book
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
Book
VLSI Test Principles and Architectures: Design for Testability
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
Proceedings ArticleDOI
Verification of large synthesized designs
TL;DR: The problem of checking equality of Boolean functions can be solved successfully using existing techniques for only a limited range of examples, but this work extends the range by using a test generator and the divide and conquer paradigm.
Book
Electronic Design Automation: Synthesis, Verification, and Test
TL;DR: EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits.
Journal ArticleDOI
Statistical Fault Analysis
TL;DR: Among Stafan's advantages, fault coverage and the undetected fault data obtained for actual circuits are shown to agree within five percent of fault simulator results, yet CPU time and memory demands fall far short of those required in fault simulation.
References
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Proceedings ArticleDOI
A logic design structure for LSI testability
TL;DR: A logic design method that will greatly simplify problems in testing, diagnostics, and field service for LSI is described, based on two concepts that are nearly independent but combine efficiently and effectively.
Journal ArticleDOI
Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits
TL;DR: Two algorithms are presented: one, DALG-II, computes a test to detect a failure in acyclic logic circuits; the other, TEST-DETECT, ascertains all failures detected by a given test.
Proceedings ArticleDOI
Test Generation Costs Analysis and Projections
TL;DR: Empirical data is presented to support the thesis that test volume grows linearly with G for LSSD structures that cannot be partitioned into disjoint substructures.
Journal ArticleDOI
9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits
TL;DR: An algorithm for generating test patterns for combinational circuits has been developed and programmed and finds a test for all faults including those that require multiple paths to be sensitized, by sensitizing a single path at a time and trying at most each single path.
Journal ArticleDOI
An Algorithm for the Generation of Test Sets for Combinational Logic Networks
TL;DR: An algorithm is developed for generating a single-fault detection test set to be used in a combinational logic network that generates a test set rather than a single test, which is based on a previous test.