Proceedings ArticleDOI
An accurate PLL behavioral model for fast Monte Carlo analysis under process variation
Chin-Cheng Kuo,Meng-Jung Lee,I-Ching Tsai,Chien-Nan Jimmy Liu,Ching-Ji Huang +4 more
- pp 110-114
TLDR
An accurate behavioral Monte Carlo simulation (BMCS) approach to analyze PLL designs under process variation is developed by building a bottom-up behavioral modeling approach with an efficient extraction process to provide accurate enough results with less regression cost.Abstract:
Hierarchical statistical analysis using the regression-based approach is often used to improve the extremely expensive HSPICE Monte Carlo (MC) analysis. However, accurately fitting the regression equations requires many simulation samples. In this paper, an accurate behavioral Monte Carlo simulation (BMCS) approach to analyze PLL designs under process variation is developed by building a bottom-up behavioral modeling approach with an efficient extraction process. Using the accurate model, we also develop a modified sensitivity analysis for process variation effects to provide accurate enough results with less regression cost. As shown in the experimental results, we reduce the simulation time of HSPICE MC analysis from several weeks to several hours and still retain similar statistical results as in HSPICE MC simulation.read more
Citations
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Proceedings ArticleDOI
A Phase-Locked Loop reference spur modelling using Simulink
TL;DR: Charge pump and Phase/Frequency Detector non-idealities are introduced in the integer-N PLL behavioural model to estimate the periodic noise, which is also known as reference spurs.
Proceedings ArticleDOI
PLL lock time prediction and parametric testing by lock waveform characterization
TL;DR: This method uses either an Automatic Test Equipment or on-chip Digital Signal Processor to compute FFT values for the lock waveform which is then used for lock time prediction and includes parametric fault coverage in addition to catastrophic fault coverage without any significant test time overhead.
Proceedings ArticleDOI
A new all-digital phase-locked loop based on single CPLD
Weicong Shen,Fan Zhang +1 more
TL;DR: A new all-digital phase-locked loop (ADPLL) is presented, which locks phase faster and the frequency range of the input signal is wider.
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