Open AccessJournal Article
An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors
TLDR
In this paper, a frequency-synthesizing, all-digital phase-locked loop (ADPLL) is integrated with a 0.5 μm CMOS microprocessor.Abstract:
A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 μm CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4× the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fsread more
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A low-noise fast-lock phase-locked loop with adaptive bandwidth control
Joonsuk Lee,Beomsup Kim +1 more
TL;DR: A salient analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status and the phase error amount that achieves fast locking and minimizes output jitters.
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Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process
TL;DR: The presented ideas enable the employment of fully-digital frequency synthesizers using sophisticated signal processing algorithms, realized in the most advanced deep-submicrometer digital CMOS processes which allow almost no analog extensions.
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A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI
TL;DR: An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully programmable PID loop filter and features a third order delta sigma modulator as discussed by the authors.
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An all-digital phase-locked loop for high-speed clock generation
Ching-Che Chung,Chen-Yi Lee +1 more
TL;DR: An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented and can easily be ported to different processes in a short time, making it very suitable for system-on-chip applications.
Journal ArticleDOI
A digitally controlled PLL for SoC applications
Tommy Olsson,Peter M. Nilsson +1 more
TL;DR: The next version of this all-digital PLL is described in synthesizable VHDL code, which simplifies digital system simulation and change of process and a new time-to-digital converter with higher resolution is designed for the improved PLL.