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Journal ArticleDOI

An Improved Capacitance-to-Digital Converter for Leaky Capacitive Sensors

09 Jul 2015-IEEE Sensors Journal (IEEE)-Vol. 15, Iss: 11, pp 6238-6247
TL;DR: A capacitance-to-digital converter that employs a novel approach to perform an accurate measurement of capacitance of a leaky capacitive sensor and gives much higher update rate compared with the IDC as it requires only a few excitation cycles for the conversion, but still gives an accurate output.
Abstract: This paper presents a capacitance-to-digital converter (CDC) that employs a novel approach to perform an accurate measurement of capacitance of a leaky capacitive sensor. This CDC employs a sinusoidal source for excitation, which is advantageous for various sensing applications, including ice detection, liquid level measurement, humidity measurement, proximity sensing, and so on. Recently, an impedance-to-digital converter (IDC) based on the dual-slope conversion technique has been reported. It can measure the value of capacitance even when a parallel resistance is present, but requires a large number of sinusoidal excitation cycles to complete a conversion, leading to poor update rate. The CDC proposed in this paper gives much higher (about 125 times) update rate compared with the IDC as it requires only a few excitation cycles for the conversion, but still gives an accurate output due to the use of a specially designed clock, which helps to count the number of charge packets received by the integrator capacitor during the deintegration. Other than the operation of the CDC, this paper also describes an outcome of a thorough analysis conducted to quantify the effect of various circuit parameters on the output of the new CDC. A prototype of the improved CDC has been developed, and its performance parameters, such as accuracy (±0.27%), conversion time (24 ms), effect of parallel resistance, and so on, have been tested, and the results are reported in this paper.
Citations
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Journal ArticleDOI
30 May 2019
TL;DR: An accurate impedance-to-time converter (ITC) circuit for leaky capacitive sensors that is able to deal with these problems and estimate the sensor capacitor and leaky resistor is presented in this article.
Abstract: Capacitive sensors suffer from problems of the parasitic and offset capacitors. Also, in some capacitive sensors, leaky resistors carry information along with the sensor capacitor. An accurate impedance-to-time converter (ITC) circuit for leaky capacitive sensors that is able to deal with these problems and estimate the sensor capacitor and leaky resistor is presented in this article. The proposed circuit is a modified relaxation oscillator, which combines dual slope and charge transfer methods to measure the sensor capacitor and leaky resistor. The output pulses of the oscillator are acquired, and pulsewidth corresponding to high and low pulse are extracted and averaged. The effect of dc errors and jitter are significantly reduced because of the averaging. A prototype of the proposed ITC has been developed and tested. Experimental results show that the proposed ITC can measure low values of the sensor capacitor (minimum 9.6 pF) in the presence of a wide range of leaky resistors (270 kΩ to 9.6 MΩ) and offset capacitors (9.6 pF to 543.4 pF) with a worst-case error of about 1.1%, as compared to the theoretical values. The targeted application for the designed circuit is the humidity sensor with a frequency range between 500 Hz and 5 kHz.

25 citations


Cites background or methods from "An Improved Capacitance-to-Digital ..."

  • ...The circuits presented in [11] and [18] can also handle leakage up to 10 M , but the minimum value of Cx measurement is one decade less than the proposed circuit....

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  • ...Dual slopebased capacitance-to-digital converters, implemented using switchbased PSD, are reported in [10] and [11]....

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Journal ArticleDOI
TL;DR: An autonulling-based multimode impedance-to-voltage converter (AN-Z2V) signal conditioning circuit for resistive–capacitive (R-C) sensors that takes advantage of the reuse of the phase tracking and aut onulling modules to extract the in-phase and quadrature components of the sensors.
Abstract: In this article, we propose an autonulling-based multimode impedance-to-voltage converter (AN-Z2V) signal conditioning circuit for resistive–capacitive (R-C) sensors. The proposed technique takes advantage of the reuse of the phase tracking and autonulling modules to extract the in-phase and quadrature components of the sensors. The circuit is designed for three sensing modes: 1) Mode-C for capacitive sensors with leakage resistor; 2) Mode-R for resistive sensors with parasitic shunt capacitor; and 3) Mode-Z for impedance R-C sensor. A novel autotuning quadrature phase generator circuit is designed and implemented for the generation of reference 90° phase-shifted signal for the leaky capacitive sensors. A prototype of the proposed circuit is fabricated and tested. Measurement results show that AN-Z2V provides the measurement range with low relative error compared with the reported systems. The system is tested for a range of 10–760 pF and 56 $\text{k}\Omega $ –6.5 $\text{M}\Omega $ for mode-C and mode-R, respectively. The accuracy of the proposed circuit is found to be ±0.11% and ±0.07% for mode-C and mode-R, respectively. The capacitance and resistance of the impedance R-C sensor are simultaneously measured in mode-Z for a range of 33–528 pF and 100 $\text{k}\Omega $ –7.8 $\text{M}\Omega $ , respectively.

14 citations


Cites background or methods from "An Improved Capacitance-to-Digital ..."

  • ...The frequency dependence of the phase shift of the all-pass filter circuit utilized in [13] affects the robustness of the circuit against the variation in the input signal frequency....

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  • ...The circuit presented in [13] utilizes a PSD technique followed by a dual-slope ADC to measure the sensor capacitance of the leaky capacitive sensors....

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Journal ArticleDOI
TL;DR: In this paper, the authors proposed an auto-balancing capacitance-to-pulsewidth converter (CPC) that uses sinusoidal excitation, and operates in a closed-loop configuration.
Abstract: A novel auto-balancing capacitance-to-pulse-width converter (CPC) that uses sinusoidal excitation, and operates in a closed-loop configuration, is presented in this paper. Unlike most of the existing CPCs, the proposed interface circuit is compatible with both single-element and differential capacitive sensors. In addition, it provides a pulse-width modulated (PWM) signal which can easily be digitized using a counter. From this PWM signal, a ratio output is derived when a single-element sensor is interfaced, and a ratiometric output is obtained for a differential sensor. The final digital output is independent of the nominal capacitance of the sensor and has a linear characteristic irrespective of the sensor characteristic being linear or inverse. The CPC is designed such that the PWM output depends on the change in the sensor capacitance alone. It is insensitive to parasitic capacitance and has very low sensitivity to the non-idealities of the components and ICs used. The effects due to some of the non-idealities are automatically corrected by the negative feedback based auto-balancing employed. The effect of component mismatch is significantly reduced by a one-time correction mechanism. These benefits are achieved without the use of any complex or expensive analog building blocks. The prototype exhibits a maximum non-linearity error of less than 0.7%, a resolution of 13.02 effective number of bits (ENOB), a signal-to-noise ratio (SNR) of 80.12 dB, and a rise time of 5 ms. Thus, the proposed simple, yet effective, low-power, low cost, auto-balancing CPC can be used to interface a wide range of existing and new capacitive sensors to digital systems

12 citations


Cites background or methods from "An Improved Capacitance-to-Digital ..."

  • ...Although the methods in [33] and [37] use sine wave excitation, [33] is suitable only for single-element capacitive sensors....

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  • ...In addition, [33] requires a very special clock to achieve good linearity, adding to its complexity, cost, and...

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Journal ArticleDOI
TL;DR: The design and implementation of an adaptable field-programmable gate array (FPGA)-based sensor evaluation platform to benchmark a capacitive position sensor for a resonant micromirror system is presented.
Abstract: We present the design and implementation of an adaptable field-programmable gate array (FPGA)-based sensor evaluation platform. This platform is developed to benchmark a capacitive position sensor for a resonant micromirror system. The sensor is developed in a smart packaging solution as a multilayer inkjet-printed electrode structure on a 3-D-printed metal housing. Very high required resolutions of respos $r_{m} = {1000}~\mu \text{m}$ at an offset of $d_{0} ={1000}~\mu \text{m}$ , motivate the development of such a platform. Yet, it is fully adaptable to other sensing principles (e.g., inductive). The suggested platform provides high sampling rates (up to ${\approx} {10}$ ns) and enables generation of trigger signals, i.e., the mirror control signal, without time lag (as could result from high-order filters). The online configurable FPGA block structure in combination with host software blocks enables flexible and individual design. The sensor read-out circuitry is designed as a carrier frequency system. Such a carrier frequency system enables flexible choices of bandwidth and measurement signal frequency. It thus allows for separation in frequency from coupling parasitics, i.e., other frequencies present in the device under test (e.g., actuation frequency in case of the micromirror system).

11 citations

References
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Book
01 Aug 1996
TL;DR: Capacitive sensors in Silicon Technology as discussed by the authors have been shown to have high dielectric properties of various materials, including electret microphones, acceleration sensors, and sensors with different types of connectors.
Abstract: Preface Introduction Electrostatics Capacitive Sensor Basics Circuit Basics APPLICATIONS Capacitive Micrometers Proximity Detectors Motion Encoders Multiple Plate Systems Miscellaneous Sensors DESIGN Circuits and Components Switched Capacitor Techniques Noise and Stability Hazards PRODUCTS Electret Microphone Accelerometer StudSensor Proximity Detector Vernier Caliper Graphic Input Tablet Camera Positioner Digital Level References Appendix 1--Capacitive Sensors in Silicon Technology Appendix 2--Dielectric Properties of Various Materials Index

695 citations


"An Improved Capacitance-to-Digital ..." refers background in this paper

  • ...CAPACITIVE sensors are widely accepted in the industry for many applications such as flow measurement [1], [2], level measurement [3], proximity detection [4], [5], measurement of humidity [6], [7], detection of ice layer [8],...

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Book
17 Aug 1993
TL;DR: Signal Conditioning for Resistive Sensors Reactance Variation and Electromagnetic Sensors and Signals for Self-Generating Sensors Signal conditioning for self-Generation Sensors Digital Sensors Telemetry and Data Acquisition.
Abstract: Resistive Sensors Signal Conditioning for Resistive Sensors Reactance Variation and Electromagnetic Sensors Signal Conditioning for Reactance Variation Sensors Generating Sensors Signal Conditioning for Self-Generating Sensors Digital Sensors Other Sensing Methods Telemetry and Data Acquisition General Bibliography Appendix Index.

432 citations


"An Improved Capacitance-to-Digital ..." refers background in this paper

  • ...CAPACITIVE sensors are widely accepted in the industry for many applications such as flow measurement [1], [2], level measurement [3], proximity detection [4], [5], measurement of humidity [6], [7], detection of ice layer [8],...

    [...]

01 Jan 2016

206 citations


"An Improved Capacitance-to-Digital ..." refers background or methods in this paper

  • ...Similarly, the effect of the offset voltage of OA2, VOS2, can be found by replacing ±VOS with ∓VOS2 in Nε and it was also found to be negligible....

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  • ...The signal vo2 is obtained as vo2 = −vo1 through an inverting amplifier formed using the opamp OA2 and two resistors (RA) as shown in Fig....

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  • ...The effect of the input bias currents IN2 of OA2 and IN of OA can be analyzed by replacing VOS with ∓IN2 RA/2 and IN RI respectively in Nε ....

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  • ...Thus, the Slew Rate (SR) of the opamp OA3 should be such that it satisfies the criteria, Vm f ≤ S R/2π [26]....

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  • ...The opamps OA, OA1, OA2, OA3 were realized using low offset opamp IC OPA277....

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Journal ArticleDOI
TL;DR: A new smart interface based on a first-order charge-balanced SC-oscillator is presented for capacitive sensors, which are shunted by a parasitic conductance, and the effect of shunting conductance is reduced by using the charge/discharge method.
Abstract: A new smart interface based on a first-order charge-balanced SC-oscillator is presented for capacitive sensors, which are shunted by a parasitic conductance. In the novel interface, the effect of shunting conductance is reduced by using the charge/discharge method. The effect of the stray capacitances is eliminated by using the two-port measurement. Moreover, all multiplicative and additive errors of the interface are also eliminated by using the auto-calibration technique and the chopping technique.

97 citations


"An Improved Capacitance-to-Digital ..." refers background or methods in this paper

  • ...The schemes in [17] and [18] are based on a relaxation oscillator circuit....

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  • ...In [17], the effect of Rp (>1 M ) is reduced using a three signal auto-calibration technique....

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  • ...The value of Rp is influenced by several environmental factors [17], [18] such as humidity, pollution, etc....

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Journal ArticleDOI
TL;DR: An analog-to-digital converter is developed based on the charge-balancing principle that consists of a switched-capacitor integrator, comparator, and digital logic circuit.
Abstract: An analog-to-digital converter is developed based on the charge-balancing principle. It consists of a switched-capacitor integrator, comparator, and digital logic circuit. Driven by the two phase clock, the integrator accumulates consecutively the incremental signal charge while extracting the quantized reference charge from the accumulated signal charge each time its output becomes positive, to keep their charge balance. The ratio between the accumulated and extracted frequencies for a given period of time then provides the digital representation of an input analog signal. A conversion accuracy higher than 14 bits can be expected from its integrated realization because the offset voltage and the finite open-loop gain of an op-amp and the parasitic capacitance have no effect upon the conversion process. It also features a small device-count integrate onto a very small chip area. Some applications are also presented to demonstrate its validity.

90 citations


"An Improved Capacitance-to-Digital ..." refers background or methods in this paper

  • ...ted [13]–[16] or available in the market gives erroneous output when a leaky capacitive sensor is employed, which has a resistance Rp in parallel to the sensor capacitance Cx ....

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  • ...principle of charge balance [13] or integrating type analogto-digital conversion [14], [15] techniques while some others...

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