An MOS transistor charge model for VLSI design

TLDR: The development of an MOS transistor charge and capacitance model for the analysis and design of VLSI circuits is described and results compare well with experimental data for transistors with channel lengths as small as 0.75 mu m.

Abstract: The development of an MOS transistor charge and capacitance model for the analysis and design of VLSI circuits is described. The total stored charge in each of the gate, bulk, and channel regions is obtained by integrating the distributed charge densities over the thin-oxide area. Charge conservation is guaranteed in this model by using the terminal charges as the state variables. The capacitance expressions have the nonreciprocal property. Partition of channel charge into the drain and source components is 40/60 in the saturation region. In the triode region, this partition changes asymptotically to 50/50 as the gate voltage increases. The carrier-velocity saturation effect is incorporated through both the modification of channel quasi-Fermi level and the determination of drain saturation voltage. Implementation of the model in the SPICE circuit simulator has been achieved. Modeled results compare well with experimental data for transistors with channel lengths as small as 0.75 mu m. >