Asymmetrical Reactive Power Capability of Modular Multilevel Cascade Converter Based STATCOMs for Offshore Wind Farm
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Citations
Benchmarking of Modular Multilevel Converter Topologies for ES-STATCOM Realization
A Reduced Series/Parallel Module for Cascade Multilevel Static Compensators Supporting Sensorless Balancing
ADMM-based distributed optimal reactive power control for loss minimization of DFIG-based wind farms
Machine Learning Based Operating Region Extension of Modular Multilevel Converters Under Unbalanced Grid Faults
A DC-Link Capacitor Voltage Ripple Reduction Method for a Modular Multilevel Cascade Converter With Single Delta Bridge Cells
References
Grid Converters for Photovoltaic and Wind Power Systems
Dual current control scheme for PWM converter under unbalanced input voltage conditions
Modeling and Control of a Modular Multilevel Converter-Based HVDC System Under Unbalanced Grid Conditions
Multilevel Converters: Fundamental Circuits and Systems
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Frequently Asked Questions (12)
Q2. What are the future works mentioned in the paper "Aalborg universitet asymmetrical reactive power capability of modular multilevel cascade converter based statcoms for offshore wind farm tanaka," ?
As a future work, asymmetrical faulty grid voltage recovering performance of the DSBC based STATCOM by negative-sequence reactive current injection will be studied, which becomes most advanced requirement emerging in a European country as an optional code.Β
Q3. What are the electrical losses of the power semiconductor modules?
The electrical losses of the power semiconductor modules consist of the conduction loss of the IGBTs, turn on / off loss of the IGBTs, conduction loss ofthe Diodes, and recovery loss of the Diodes in the power modules.Β
Q4. What is the dc-bias voltage in the MMCC-DSCC?
due to the voltage balancing control, the VβPN is required, which can be expressed asπππ β² = πΌπ·ππ΅πΆπππ (32)where DSBC is the amplitude ratio of the differential voltage between terminal P and N of the DSCC to the DSBC.Β
Q5. Why is the peak junction temperature smaller than the DSCC?
the amplitude of the PWM output voltage with dc-component is smaller than the DSCC because of avoiding the voltage saturation of each cell output voltage command.Β
Q6. How is the voltage of the power semiconductor module simulated?
The electrical losses and junction temperatures on each power semiconductor module are simulated by thermal simulation function on the PLECS.Β
Q7. What is the nominal output voltage of each converter cell?
The nominal output AC voltage each converter cell in the SSBC, SDBC and DSBC is designed at 1450 Vrms with the nominal modulationfactor n = 0.8.Β
Q8. What is the MMCC-SSBC with zero-sequence AC voltage?
The MMCC-SSBC with zero-sequence AC voltageWhere the zero-sequence AC voltage with the samefrequency as the phase-cluster current is injected, the zero-sequence voltage and the cluster current formulate thedifferent active power between the clusters in theMMCC-SSBC.Β
Q9. What is the voltage command and junction temperature?
The peak voltage command and junction temperature are normalized by instantaneous dc-link voltage each cell converter and temperature limitation value decided by the manufacturer as mentioned in the sub-section V-B, C, and D.Β
Q10. What is the over current level of the DSBC?
The over current level becomes lower than the SDBC because the current distribution between the IGBT modules in a converter cell increases by injected dc voltage and current for the capacitor voltage balancing method.Β
Q11. What is the maximum arm r.m.s. current?
The maximum arm r.m.s. current increases moderate in respect to the D, but reach the over current level (1.07) which is decided by the over junction temperature of the IGBT module, which is shown next chapter.Β
Q12. What is the peak voltage command and peak junction temperature of the MMCC-SSBC?
It can be noted that the peak value of the cluster current increases by maximum 52% at the v and w cluster under the phase-to-phase fault in order to inject zero-sequence current izero to balance the DC-link capacitorFig. 14 shows the maximum peak voltage command and peak junction temperature among the cells for different dip severities D under the various grid fault scenarios.Β