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Open AccessProceedings ArticleDOI

Automatic instrumentation of embedded software for high level hardware/software co-simulation

TLDR
The proposed “cross-annotation” technique consists of extending a retargetable compiler infrastructure to allow the automatic instrumentation of embedded software at the basic block level, and takes into account the processor-specific optimizations at the compiler level.
Abstract
We propose an automatic instrumentation method for embedded software annotation to enable performance modeling in high level hardware/software co-simulation environments. The proposed "cross-annotation" technique consists of extending a retargetable compiler infrastructure to allow the automatic instrumentation of embedded software at the basic block level. Thus, target and annotated native binaries are guaranteed to have isomorphic control flow graphs (CFG). The proposed method takes into account the processor-specific optimizations at the compiler level and proves to be accurate with low simulation overhead.

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Proceedings ArticleDOI

Fast and accurate source-level simulation of software timing considering complex code optimizations

TL;DR: Experimental results show that the presented method produces timing estimates within the same level of accuracy as an established commercial tool for cycle-accurate instruction set simulation while being at least 20 times faster.
Proceedings ArticleDOI

Automated, retargetable back-annotation for host compiled performance and power modeling

TL;DR: A novel host-compiled simulation approach that provides close to cycle-accurate estimation of energy and timing metrics in a retargetable manner, using flexible, architecture description language (ADL) based reference models is proposed.
Proceedings ArticleDOI

Native MPSoC co-simulation environment for software performance estimation

TL;DR: A transactional level simulation environment that allows reliable performance estimation with a specific focus on software timing estimation on multi processor architectures and the use of both static and dynamic analysis, that allow realistic timing measurements in native software simulation is presented.
Proceedings ArticleDOI

Abstract system-level models for early performance and power exploration

TL;DR: In this article, the authors present ingredients for a class of abstract, high-level platform models that enable fast yet accurate performance and power simulation of application execution on heterogeneous multi-core/processor architectures.
Proceedings ArticleDOI

Sampling-based program execution monitoring

TL;DR: This work presents a sampling-based approach to execution monitoring which specifically helps developers debug time-sensitive systems such as real-time applications and designs seven heuristics and an instrumentation framework to extend the sampling period which can reduce the monitoring overhead and achieve an optimal tradeoff between accuracy and overhead introduced by instrumentation.
References
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Proceedings ArticleDOI

LLVM: a compilation framework for lifelong program analysis & transformation

TL;DR: The design of the LLVM representation and compiler framework is evaluated in three ways: the size and effectiveness of the representation, including the type information it provides; compiler performance for several interprocedural problems; and illustrative examples of the benefits LLVM provides for several challenging compiler problems.
Proceedings ArticleDOI

MiBench: A free, commercially representative embedded benchmark suite

TL;DR: A new version of SimpleScalar that has been adapted to the ARM instruction set is used to characterize the performance of the benchmarks using configurations similar to current and next generation embedded processors.
Proceedings ArticleDOI

A generic RTOS model for real-time systems simulation with systemC

TL;DR: This paper presents a generic model of RTOS based on systemC that allows assessing real-time performances and the influence of scheduling according to RTOS properties such as scheduling policy, context-switch time and scheduling latency.
Proceedings ArticleDOI

Cycle-approximate retargetable performance estimation at the transaction level

TL;DR: A novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multi-core designs and it produces high-speed native compiled TLMs that are close to cycle-accurate and can be applied to any multi- core platform.
Proceedings ArticleDOI

Reliable estimation of execution time of embedded software

TL;DR: A technique based upon a statistical approach that improves existing estimation techniques is described that provides a degree of reliability in the error of the estimated execution time of embedded software.
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