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Cache-aware scheduling and analysis for multicores

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TLDR
A scheduling strategy for real-time tasks with both timing and cache space constraints is presented, which allows each task to use a fixed number of cache partitions, and makes sure that at any time a cache partition is occupied by at most one running task.
Abstract
The major obstacle to use multicores for real-time applications is that we may not predict and provide any guarantee on real-time properties of embedded software on such platforms; the way of handling the on-chip shared resources such as L2 cache may have a significant impact on the timing predictability. In this paper, we propose to use cache space isolation techniques to avoid cache contention for hard real-time tasks running on multicores with shared caches. We present a scheduling strategy for real-time tasks with both timing and cache space constraints, which allows each task to use a fixed number of cache partitions, and makes sure that at any time a cache partition is occupied by at most one running task. In this way, the cache spaces of tasks are isolated at run-time.As technical contributions, we have developed a sufficient schedulability test for non-preemptive fixed-priority scheduling for multicores with shared L2 cache, encoded as a linear programming problem. To improve the scalability of the test, we then present our second schedulability test of quadratic complexity, which is an over approximation of the first test. To evaluate the performance and scalability of our techniques, we use randomly generated task sets. Our experiments show that the first test which employs an LP solver can easily handle task sets with thousands of tasks in minutes using a desktop computer. It is also shown that the second test is comparable with the first one in terms of precision, but scales much better due to its low complexity, and is therefore a good candidate for efficient schedulability tests in the design loop for embedded systems or as an on-line test for admission control.

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Citations
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Scheduling and locking in multiprocessor real-time operating systems

TL;DR: The experiments show that partitioned earliest-deadline first (EDF) scheduling is generally preferable in a hard real- time setting, whereas global and clustered EDF scheduling are effective in a soft real-time setting.
Journal ArticleDOI

Building timing predictable embedded systems

TL;DR: The intention of this article is to summarize the current state of the art in research concerning how to build predictable yet performant systems, and suggest precise definitions for the concept of “predictability”, and present predictability concerns at different abstraction levels in embedded system design.
Proceedings ArticleDOI

A Coordinated Approach for Practical OS-Level Cache Management in Multi-core Real-Time Systems

TL;DR: A practical OS-level cache management scheme for multi-core real-time systems that provides predictable cache performance, addresses the aforementioned problems of existing software cache partitioning, and efficiently allocates cache partitions to schedule a given task set is proposed.
Proceedings ArticleDOI

Combining Abstract Interpretation with Model Checking for Timing Analysis of Multicore Software

TL;DR: A tool for multicore timing analysis is developed that allows automatic generation of the TA models from binary code and WCET estimation for any given TA model of the shared bus, and the combined approach can significantly tighten the estimations.
Proceedings ArticleDOI

Timing Analysis for TDMA Arbitration in Resource Sharing Systems

TL;DR: The worst-case completion time for real-time tasks when time division multiple access (TDMA) policies are applied for resource arbitration is analyzed, for a given TDMA arbiter.
References
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Proceedings ArticleDOI

Preemptive Scheduling of Multi-criticality Systems with Varying Degrees of Execution Time Assurance

TL;DR: This paper presents ways to use information from a conjecture that the more confidence one needs in a task execution time bound, the larger and more conservative that bound tends to become in practice.
Proceedings ArticleDOI

An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches

TL;DR: This paper proposes physical designs for these Non-Uniform Cache Architectures (NUCAs) and extends these physical designs with logical policies that allow important data to migrate toward the processor within the same level of the cache.
Proceedings ArticleDOI

Predicting inter-thread cache contention on a chip multi-processor architecture

TL;DR: Three performance models are proposed that predict the impact of cache sharing on co-scheduled threads and the most accurate model, the inductive probability model, achieves an average error of only 3.9%.
Proceedings ArticleDOI

Static-priority scheduling on multiprocessors

TL;DR: In this paper, a static-priority scheduling algorithm is proposed for static priority scheduling of systems of periodic tasks on a platform comprised of several identical processors, and it is proven that this algorithm successfully schedules any periodic task system with a worst-case utilization no more than a third the capacity of the multiprocessor platform.
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