Proceedings ArticleDOI
ChADD: An ADD Based Chisel Compiler with Reduced Syntactic Variance
Vikas Chauhan,Neel Gala,V. Kamakoti +2 more
- pp 499-504
TLDR
It is shown that for a given design, two different styles of Chisel implementations yield the same target net list, thereby ensuring syntactic invariance, and it is shown empirically that the net list generated by the proposed technique is equally competitive to the most optimal net listgenerated by the conventional compiler while targeting an FPGA.Abstract:
The need for quick design space exploration and higher abstracted features required to design complex circuits has led designers to adopt High Level Synthesis languages (HLS) for hardware generation. Chisel is one such language, which offers majority of the abstraction facilities found in today's software languages and also guarantees synthesizability of the generated hardware. However, most of the HLS languages, including Chisel, suffer from syntactic variance and thus the hardware inferred by these languages are inconsistent and rely heavily on the description styles used by the designer. Thus semantically equivalent circuit descriptions with different syntax can lead to different hardware utilization. In this paper, we propose the use of ADDs (Assignment Decision Diagrams) as an intermediate representation between Chisel and the target net list representation. Following this path we have shown that for a given design, two different styles of Chisel implementations yield the same target net list, thereby ensuring syntactic invariance. For the same design implementations the conventional Chisel compiler reports significant syntactic variance. In addition, we show empirically that the net list generated by the proposed technique is equally competitive to the most optimal net list generated by the conventional compiler while targeting an FPGA, implying that different implementations leads to close to optimal solutions.read more
Citations
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Patent
Generation method of optimal net list for functional simulation of large-capacity FPGA (Field Programmable Gate Array) circuit
TL;DR: In this article, an optimal net list for functional simulation of a large-capacity FPGA (Field Programmable Gate Array) circuit is generated by dynamically configuring the net list and can save simulation resources; the operation speed and the validation efficiency of a simulator are improved and the coverage rate of a validation circuit is improved.
References
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Book
High ― Level Synthesis: Introduction to Chip and System Design
TL;DR: This paper presents a methodology for High-Level Synthesis of Architectural Models in Synthesis and its applications in Design Description Languages and Design Representation and Transformations.
Proceedings ArticleDOI
Chisel: constructing hardware in a Scala embedded language
Jonathan Bachrach,Huy Vo,Brian Richards,Yunsup Lee,Andrew Waterman,Rimas Avizienis,John Wawrzynek,Krste Asanovic +7 more
TL;DR: Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages, is introduced by embedding Chisel in the Scala programming language, raising the level of hardware design abstraction.
Proceedings ArticleDOI
Bluespec System Verilog: efficient, correct RTL from high level specifications
TL;DR: By means of code samples, demonstrations and measured results, it is illustrated how Bluespec System Verilog, in an environment familiar to hardware designers, can significantly improve productivity without compromising generated hardware quality.
Journal ArticleDOI
Rethinking Digital Design: Why Design Must Change
Ofer Shacham,Omid Azizi,Megan Wachs,Wajahat Qadeer,Zain Asgar,Kyle Kelley,John P. Stevenson,Stephen Richardson,Mark Horowitz,Benjamin C. Lee,Alex Solomatnikov,Amin Firoozshahian +11 more
TL;DR: Domain-specific chip generators are templates that codify designer knowledge and design trade-offs to create different application-optimized chips to reduce design costs.
Journal ArticleDOI
Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams
Indradeep Ghosh,M. Fujita +1 more
TL;DR: An algorithm for generating test patterns automatically from functional register-transfer level (RTL) circuits that target detection of stuck-at faults in the circuit at the logic level, using a data structure named assignment decision diagram that has been proposed previously in the field of high-level synthesis.