Characterization of multiple deep level systems in semiconductor junctions by admittance measurements

TLDR: In this article, the small signal admittance of a junction device in the presence of deep lying majority carrier traps is obtained as a solution to a simple differential equation (dC/dχ) = (C2/e)−(ρac/ψac), where C Y/jω is the complex capacitance, x is the distance within the depletion region from the neutral bulk semiconductor, ρac is the a.c. incremental change in charge density at χ when the bias is incremented by ψac.

Abstract: The small signal admittance, Y, of a junction device, in the presence of deep lying majority carrier traps, is obtained as a solution to a simple differential equation (dC/dχ) = (C2/e)−(ρac/ψac), where C Y/jω is the complex capacitance, x is the distance within the depletion region from the neutral bulk semiconductor, ρac is the a.c. incremental change in charge density at χ when the bias is incremented by ψac. This equation can be numerically integrated with one boundary condition, the flat band capacitance of the bulk semiconductor. An analytic solution to the above differential equation is possible over a wide frequency range without the use of a truncated space charge approximation. The admittance of one half of a junction device can then be modelled by a 3p + 1 lumped element equivalent circuit involving 3p + 2 device parameters, where p is the number of species of deep lying majority carrier traps that are virtually unionized in the bulk. These circuit elements bear simple direct relationships to the deep level parameters. Impedance vs frequency measurements at a single bias and temperature yield only 2p + 1 equations and are not sufficient to define the elements uniquely. One therefore needs p + 1 additional equations for a unique synthesis. We also show how additional equations can be obtained from impedance vs voltage or temperature measurements.