Patent
Circuit for generating non-overlapping two-phase clocks
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TLDR
In this article, a clock generator for providing two clock signals for use with two-phase flip-flops, consisting of a settable latch and a gating device, is presented.Abstract:
In order to provide for clocking master/slave flip-flops in complex circuits by means of non-overlapping two-phase clocks, a clock generator for providing two clocks signals for use with two-phase flip-flops, comprises a settable latch and a gating device. The settable latch has a data input connected to a reference source, a set input connected to receive one of the two clock signals and a clock input connected to receive the other of the two clock signals. The gating device has one input connected to receive such one of the two clock signals and a second input connected to the output of the settable latch. The output of the gating device, which corresponds to the other of the two clock signals, is connected to the clock input of the settable latch, the arrangement being such that when the settable latch has been set by a transition of the one clock signal resetting of the settable latch is enabled by the other clock signal. A digital circuit, for example an integrated circuit, may have a number of latches, each comprising, for example the first stage of a master/slave flip-flop, and such a clock generator for operating them. Preferably the latches are arranged in groups, conveniently as a macro sub-block, with a clock generator for operating each group. Preferably the settable latch is similar in construction to the latches being controlled.read more
Citations
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References
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Journal ArticleDOI
Design and analysis of a hierarchical clock distribution system for synchronous standard cell/macrocell VLSI
Eby G. Friedman,S. Powell +1 more
TL;DR: The advantages and disadvantages of a hierarchical design technique for minimizing clock skew within a VLSI circuit are discussed and a model for clock distribution networks which considers the effects of distributed interconnect impedances on clock skew is described.
Patent
Clock generator circuit
TL;DR: In this article, a clock generator circuit for an integrated circuit which is controlled by clock signals obtained by frequency-dividing a standard clock is presented, where three flip-flops, two of which are connected in series, and two logical gates together form a synchronization circuit such that when a command signal is inputted to start testing the integrated circuit, frequency-divided clock signals in synchronism with the standard clock are outputted.
Patent
Digital waveform generator with adjustable time shift and automatic phase control
TL;DR: In this paper, a circuit for generating two pulse waveforms having a desired time and phase relationship, and an optically pumped magnetometer utilizing that circuit, was presented, where a synchronization signal toggles a bistable multivibrator to provide one pulse waveform.