A method for applying Tracey's procedure to the state assignment problem of nonnormal mode flow tables is proposed.

Comment on "Delay-Free Asynchronous Circuits with Constrained Line Delays"

The concept of the two-dimensional (2-D) parallel computer with square module arrays was first introduced by Unger. It is the purpose of this paper to discuss the relative merits of square and hexagonal module arrays, to propose an operational symbolism for the various basic hexagonal modular transformations which may be performed by these comupters, to illustrate some logical circuit implementation, and to describe a few elementary applications.

Hexagonal Parallel Pattern Transformations

The paper presents three procedures for coding the internal states of asynchronous sequential switching circuits. Resulting codes insure that the circuit will function according to flow table specifications independent of variations in transmission delays within the circuit. The assignment methods produce codes that allow one to maximize the operating speed of the circuit and are applicable to completely or incompletely specified sequential machines.

Internal State Assignments for Asynchronous Sequential Machines

Armstrong, Friedman, and Menon have shown how fundamental-mode normal flow tables can be realized without delay elements under the constraint that line delays do not exceed a given chain of gate delays. The state assignments for these tables are designed to yield noncritical races and minimum transition times. This note presents an independently discovered alternative to their design procedure and also extends their results to totally sequential (or race-free) state assignments. The almost totally sequential state assignment is defined and presented as an approach toward delay-free realizations, under suitable line delay constraints, of nonnormal flow tables.

Comment on "Delay-Free Asynchronous Circuits with Constrained Line Delays"

References

Hexagonal Parallel Pattern Transformations

Internal State Assignments for Asynchronous Sequential Machines

Delay-Free Asynchronous Circuits with Constrained Line Delays

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