Journal ArticleDOI
Conditionally robust two-pattern tests and CMOS design for testability
S.D. Sherlekar,P.S. Subramanian +1 more
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The concept of a conditionally robust two- pattern test for testing stuck-open transistor faults in CMOS gates is introduced and algorithms are given to determine whether a two-pattern test is conditionally hazard-free under a given partial order and to compute minimal cardinality partial orders that, when imposed on a transition, make it conditionallyhazard-free.Abstract:
The concept of a conditionally robust two-pattern test for testing stuck-open transistor faults in CMOS gates is introduced. Such a test is conditionally hazard-free; i.e. the transition will not produce a hazardous output provided a (partial) order is imposed on the time instants at which the components of the input pattern undergo transition. Two sources of the existence of such a partial order are identified: (1) when a set of transistors is controlled by the same logic signal, the symbolic layout (routing) information provides the knowledge of such a partial order; and (2) multipattern tests, which may be necessary to test embedded CMOS gates, can be looked upon as two-pattern tests with an imposed partial order. Algorithms are given to determine whether a two-pattern test is conditionally hazard-free under a given partial order and to compute minimal cardinality partial orders that, when imposed on a transition, make it conditionally hazard-free. >read more
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References
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Journal ArticleDOI
Fault modeling and logic simulation of CMOS and MOS integrated circuits
TL;DR: This paper provides a methodology for creating simulator models for tri-state and other dynamic circuit elements that provide for both classical and stuck-open/stuck-on faults, and can be adopted for use on essentially any general purpose logic simulator.
Proceedings ArticleDOI
A Gate Level Model for CMOS Combinational Logic Circuits with Application to Fault Detection
TL;DR: A procedure to derive gate level equivalent circuits for CMOS combinational logic circuits is given and it is shown that tests for classical stuck-at-0 and stuck- at-1 faults in the equivalent circuit can be used to detect line stuck-At, stuck-open and stuck -on faults inThe modeled CMOS circuit.
Journal ArticleDOI
Design of Testable CMOS Logic Circuits Under Arbitrary Delays
Niraj K. Jha,Jacob A. Abraham +1 more
TL;DR: This paper presents a necessary and sufficient condition for the existence of a test set, which cannot be invalidated under arbitrary delays, for an AND-OR or OR-AND CMOS realization for any given function.
Journal ArticleDOI
A Unified Approach to Combinational Hazards
TL;DR: A transition is hazard-free iff the transient switching function is unate in the transition subcube with respect to the initial and final vertices, and a transition is hazards in feedback-free combinational circuits when the transient input variable can change more than once.