Design and verification of WISHBONE bus interface for System-on-Chip integration

TLDR: The various features of WISHBONE bus interface are presented and two types of systems have been designed which utilizes DMA master cores and memory slave cores using WishBONE point-to-point and shared bus interconnection schemes and the final implementations have been done in XILINX FPGA platform.

Abstract: System-on-Chip (SOC) design is an integration of multi million transistors in a single chip for alleviating time to market and reducing the cost of the design. Design reuse — the use of pre-designed and pre-verified cores is now the cornerstone of SOC design. It uses reusable Intellectual property (IP) blocks that supports plug and play integration and in turn allows huge chips to be designed at an acceptable cost, and quality. Hence to increase the productivity with reduction in design time a standard interface bus protocol is required to perform the plug and play integration. Open core SOC design methodology utilizes WISHBONE bus interface to foster design reuse by alleviating system-on-chip integration problems. In this paper we present the various features of WISHBONE bus interface. Two types of systems have been designed which utilizes DMA master cores and memory slave cores using WISHBONE point-to-point and shared bus interconnection schemes and the final implementations have been done in XILINX FPGA platform. The functionality of the system is verified using Xilinx simulation results as well as board level ChipScope Pro results.